CSE2134 - Computer Architecture and Organizations¶

Memory and I/O¶

Q6(a) [4]: What do you mean by cache hit rate and miss rate?
Q6(c) [6]: Discuss about different mapping technique in detail.
Q7(a) [8]: Define the following addressing modes in detail with diagram: (i) Immediate addressing, (ii) Register addressing, (iii) Base or displacement addressing and (iv) PC relative addressing.
Q7(b) [4]: Give a block diagram for a \(256K \times 16\) memory module using \(64K \times 1\).

Q7(c) [5]: Draw a block diagram for a \(250k \times 16\) memory module using \(64k \times 1\).

Q5(b) [4]: What is cache memory? Define cache-hit, cache-miss and miss-penalty.
Q7(a) [6]: Give a block diagram for a \(512k \times 32\) memory module using \(128k \times 8\).
Q7(b) [3+5]: Why mapping function is needed when we use cache memory in the computer system? Explain three different mapping functions.

Q5(b) [2+3]: What is physical address and logical address? Define cache miss, hit rate, miss rate.
Q5(c) [3]: What is temporal and spatial locality?
Q6(b) [4]: Explain the write-through and write back cache handling policy.
Q7(a) [4]: What do you mean by virtual memory? Explain with example.
Q7(b) [5]: Explain three different mapping functions.

Q5(b) [6]: Explain page fault, address translation and page table.
Q6(c) [6]: Explain the proper techniques for fast address translation.
Q7(a) [5]: Why does DMA have priority over the CPU when both request a memory transfer?
Q7(b) [5]: Explain memory mapping techniques used in cache memory.
Q7(c) [4]: Write short notes on cache replacement policy and TLB.

Q3(a) [4]: Define memory hierarchy. As one goes down the hierarchy, what happens about (i) Cost per bit; (ii) Capacity; (iii) Access time; (iv) Frequency of access of the memory by the processor.
Q3(b) [6]: Explain with diagram the organization of a \(1K \times 1\) memory chip.
Q3(c) [4]: Describe the read and write operation from SRAM.
Q4(a) [2+2]: Define memory latency and bandwidth. What is the special feature of DDR SDRAM?
Q4(b) [4+2]: Explain interrupt with its hardware circuit diagram. Draw the block diagram of multiple priority interrupt unit.
Q4(c) [4]: Explain Direct Memory Access (DMA) controller with necessity diagram.
Q5(a) [6]: Suppose, main memory of a computer contains 32 blocks (0-31) and cache memory contains 8 blocks (0-7). Where does a block 15 go in the cache if direct mapped and set associative mapped are used?
Q5(b) [4]: Explain the direct-mapped and associative-mapped cache.
Q5(c) [4]: Briefly describe the memory to processor connection with necessary diagram.
Q6(c) [5]: Briefly explain the internal organisation of bit cells in memory-chips with a diagram.

Q6(a) [3]: Briefly describe the basic connection of the memory to the processor.
Q6(b) [5]: Briefly explain the internal organization of bit cells in a memory chip.
Q6(c) [6]: Design \(2M \times 32\) memory module using a \(512K \times 8\) static memory chips.
Q7(a) [2]: What is the purpose of control unit?
Q7(b) [3]: Define Word, Address, Memory Access time.