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Universal Gate implementationÂļ

🔑 Universal Logic GatesÂļ

āĻĄāĻŋāϜāĻŋāϟāĻžāϞ āϏāĻžāĻ°ā§āĻ•āĻŋāĻŸā§‡ NAND Gate āφāϰ NOR Gate āϕ⧇ āĻŦāϞāĻž āĻšā§Ÿ Universal Logic GateāĨ¤
👉 āĻ•āĻžāϰāĻŖ āĻļ⧁āϧ⧁ āĻāχ āĻĻ⧁āχ āϧāϰāύ⧇āϰ Gate āĻĻāĻŋā§Ÿā§‡āχ āϏāĻŦ Basic Logic Gate (AND, OR, NOT, XOR, XNOR) āϤ⧈āϰāĻŋ āĻ•āϰāĻž āϏāĻŽā§āĻ­āĻŦāĨ¤


🟩 NAND Universal Logic GateÂļ

Explanation of NAND

NAND āϗ⧇āϟ āϕ⧀?Âļ

NAND āϗ⧇āϟ āĻšāϞ⧋ āĻāĻ• āϧāϰāύ⧇āϰ Universal Logic GateāĨ¤ āĻāϟāĻžāϰ āĻĻ⧁āχ āĻŦāĻž āϤāĻžāϰ āĻŦ⧇āĻļāĻŋ āχāύāĻĒ⧁āϟ āĻĨāĻžāĻ•āϤ⧇ āĻĒāĻžāϰ⧇ āĻāĻŦāĻ‚ āφāωāϟāĻĒ⧁āϟ āĻĨāĻžāϕ⧇ āϏāĻŦāϏāĻŽā§Ÿ āĻāĻ•āϟāĻŋāχāĨ¤

👉 āϝāĻ–āύ āϏāĻŦ āχāύāĻĒ⧁āϟ = 1, āϤāĻ–āύ āφāωāϟāĻĒ⧁āϟ āĻšāĻŦ⧇ 0āĨ¤
👉 āĻ…āĻ¨ā§āϝ āϝ⧇āϕ⧋āύ⧋ āχāύāĻĒ⧁āϟ āĻ•āĻŽā§āĻŦāĻŋāύ⧇āĻļāύ⧇ āφāωāϟāĻĒ⧁āϟ āĻšāĻŦ⧇ 1āĨ¤

NAND Gate Basics
NAND āϗ⧇āĻŸā§‡āϰ āĻĒā§āϰāϤ⧀āĻ• (Symbol)

āĻĻ⧁āχ āχāύāĻĒ⧁āϟ NAND āϗ⧇āĻŸā§‡āϰ Truth Table āύāĻŋāĻšā§‡ āĻĻ⧇āĻ“ā§ŸāĻž āĻšāϞ⧋:

āχāύāĻĒ⧁āϟ A āχāύāĻĒ⧁āϟ B āφāωāϟāĻĒ⧁āϟ Y
0 0 1
0 1 1
1 0 1
1 1 0

Boolean Function:

\[ Y = \overline{AB} \]

āĻāĻ–āĻžāύ⧇ \(AB\)-āĻāϰ āωāĻĒāϰ āĻŦāĻžāϰ āϚāĻŋāĻšā§āύāϟāĻŋ āύāĻŋāĻ°ā§āĻĻ⧇āĻļ āĻ•āϰāϛ⧇ AND āĻāϰ āωāĻ˛ā§āĻŸā§‹ āĻŽāĻžāύ āĻŦāĻž NOT operationāĨ¤

NAND gate as NOT

NAND āϗ⧇āϟ āĻĻāĻŋā§Ÿā§‡ NOT āϗ⧇āϟ āϤ⧈āϰāĻŋ:Âļ

āĻāĻ–āύ āĻĻ⧇āĻ–āĻž āϝāĻžāĻ•, āĻ•āĻŋāĻ­āĻžāĻŦ⧇ āĻļ⧁āϧ⧁ NAND āϗ⧇āϟ āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻ•āϰ⧇ NOT Gate āĻŦāĻžāύāĻžāύ⧋ āϝāĻžā§ŸāĨ¤

NOT āϗ⧇āĻŸā§‡āϰ āφāωāϟāĻĒ⧁āϟ āĻĢāĻžāĻ‚āĻļāύ āĻšāϞ⧋:

\[ Y = \overline{A} \]

āĻ…āĻ¨ā§āϝāĻĻāĻŋāϕ⧇, NAND āϗ⧇āĻŸā§‡āϰ āφāωāϟāĻĒ⧁āϟ āĻšāϞ⧋:

\[ Y = \overline{A \cdot B} \]

👉 āϝāĻĻāĻŋ āφāĻŽāϰāĻž NAND āϗ⧇āĻŸā§‡āϰ āĻĻ⧁āχ āχāύāĻĒ⧁āϟāϕ⧇ āĻāĻ•āχ āϏāĻŋāĻ—āĻ¨ā§āϝāĻžāϞ āĻĻāĻŋāχ, āĻ…āĻ°ā§āĻĨāĻžā§Ž \(A = B = A\), āϤāĻžāĻšāϞ⧇:

\[ Y = \overline{A \cdot A} = \overline{A} \]

āĻāϟāĻžāχ āĻšāĻšā§āϛ⧇ NOT Gate-āĻāϰ āϏāĻŽāĻžāύ āφāωāϟāĻĒ⧁āϟāĨ¤

Circuit DiagramÂļ

NOT āϗ⧇āϟ NAND āϗ⧇āϟ āĻĻāĻŋā§Ÿā§‡ āĻŦāĻžāύāĻžāϤ⧇ āĻšāϞ⧇:

NAND-as-NOT
* āωāϭ⧟ āχāύāĻĒ⧁āϟāϕ⧇ āĻāĻ•āϏāĻžāĻĨ⧇ āĻļāĻ°ā§āϟ āĻ•āϰ⧇ āĻāĻ•āχ āχāύāĻĒ⧁āϟ āĻĻāĻŋāϤ⧇ āĻšāĻŦ⧇āĨ¤
* āφāωāϟāĻĒ⧁āϟ āϞāĻžāχāύ⧇ āĻĒāĻžāĻ“ā§ŸāĻž āϝāĻžāĻŦ⧇ āωāĻ˛ā§āϟāĻžāύ⧋ āĻŽāĻžāύ (Inverter Output)āĨ¤

āĻ…āĻ¨ā§āϝāĻ­āĻžāĻŦ⧇, āϝāĻĻāĻŋ āĻāĻ• āχāύāĻĒ⧁āϟāϕ⧇ Logic 1 āĻĻ⧇āĻ“ā§ŸāĻž āĻšā§Ÿ āĻāĻŦāĻ‚ āĻ…āĻ¨ā§āϝ āχāύāĻĒ⧁āĻŸā§‡ \(A\) āĻĻ⧇āĻ“ā§ŸāĻž āĻšā§Ÿ, āϤāĻžāĻšāϞ⧇āĻ“ āφāωāϟāĻĒ⧁āϟ āĻšāĻŦ⧇:

\[ Y = \overline{A \cdot 1} = \overline{A} \]

ConclusionÂļ

āφāĻŽāϰāĻž āĻĻ⧇āĻ–āϞāĻžāĻŽ āϕ⧀āĻ­āĻžāĻŦ⧇ āĻāĻ•āϟāĻŋ NAND Gate āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻ•āϰ⧇ NOT Gate āϤ⧈āϰāĻŋ āĻ•āϰāĻž āϝāĻžā§ŸāĨ¤ āϏāĻžāĻ°ā§āĻ•āĻŋāϟ āĻĄāĻžā§ŸāĻžāĻ—ā§āϰāĻžāĻŽā§‡āϰ āϏāĻžāĻšāĻžāĻ¯ā§āϝ⧇ āĻŦāĻŋāώ⧟āϟāĻŋ āφāϰāĻ“ āĻĒāϰāĻŋāĻˇā§āĻ•āĻžāϰ āĻšā§Ÿā§‡āϛ⧇āĨ¤

✅ AND Gate Using NAND GateÂļ

  • āĻĻāϰāĻ•āĻžāϰ āĻšāĻŦ⧇ 2āϟāĻž NAND gate |
  • 1āĻŽ NAND Gate → āφāωāϟāĻĒ⧁āϟ = \(\overline{A \cdot B}\) |
  • 2⧟ NAND Gate → āφāωāϟāĻĒ⧁āϟ = \(\overline{\overline{A \cdot B}} = A \cdot B\) |
  • āĻšā§‚ā§œāĻžāĻ¨ā§āϤ āφāωāϟāĻĒ⧁āϟ = AND Gate |

AND Gate Using NAND GateÂļ

✅ OR Gate Using NAND GateÂļ

((AA)'(BB)')'= (A'B')' (By Idempotent Law)
= A''+B'' (By De Morgan’s Law)
= A+B ( By involution Law)

  • āĻĻāϰāĻ•āĻžāϰ āĻšāĻŦ⧇ 3āϟāĻž NAND gate |
  • 1āĻŽ NAND Gate → āφāωāϟāĻĒ⧁āϟ = \(\overline{A}\) |
  • 2⧟ NAND Gate → āφāωāϟāĻĒ⧁āϟ = \(\overline{B}\) |
  • 3⧟ NAND Gate → āφāωāϟāĻĒ⧁āϟ = \(\overline{\overline{A} \cdot \overline{B}} = A + B\) |
  • āĻšā§‚ā§œāĻžāĻ¨ā§āϤ āφāωāϟāĻĒ⧁āϟ = OR Gate |

OR Gate Using NAND GateÂļ

✅ NOR Gate Using NAND GateÂļ

  • āĻĻāϰāĻ•āĻžāϰ āĻšāĻŦ⧇ 3āϟāĻž NAND gate |
  • 1āĻŽ NAND Gate → āφāωāϟāĻĒ⧁āϟ = \(\overline{A \cdot B}\) |
  • 2⧟ NAND Gate → āφāωāϟāĻĒ⧁āϟ = \(\overline{\overline{A \cdot B}} = A \cdot B\) |
  • 3⧟ NAND Gate → āφāωāϟāĻĒ⧁āϟ = \(\overline{(A \cdot B) \cdot (A \cdot B)} = \overline{A \cdot B}\) |
  • āĻšā§‚ā§œāĻžāĻ¨ā§āϤ āφāωāϟāĻĒ⧁āϟ = NOR Gate |

NOR Gate Using NAND Gate

XOR Gate Using NAND Gate

  • āĻĻāϰāĻ•āĻžāϰ āĻšāĻŦ⧇ 4āϟāĻž NAND gate.
  • āϧāĻžāĻĒ⧇ āϧāĻžāĻĒ⧇ āĻļ⧇āώ⧇ āφāωāϟāĻĒ⧁āϟ = \(A \oplus B\) .
  • āĻšā§‚ā§œāĻžāĻ¨ā§āϤ āφāωāϟāĻĒ⧁āϟ = XOR Gate.

XOR0-Gate-Using-NAND-Gate.png
FULL Implementation:
XOR Gate Using NAND Gate

What is a XOR Gate?Âļ

XOR (Exclusive-OR) Gate āĻšāϞ⧋ āĻāĻ• āϧāϰāύ⧇āϰ derived logic gateāĨ¤ XOR gate-āĻāϰ āĻĻ⧁āϟāĻŋ āχāύāĻĒ⧁āϟ āĻāĻŦāĻ‚ āĻāĻ•āϟāĻŋ āφāωāϟāĻĒ⧁āϟ āĻĨāĻžāϕ⧇āĨ¤ āϝāĻ–āύ āĻĻ⧁āϟāĻŋ āχāύāĻĒ⧁āĻŸā§‡āϰ āĻŽāĻ§ā§āϝ⧇ āĻāĻ•āϟāĻŋāĻŽāĻžāĻ¤ā§āϰ āχāύāĻĒ⧁āϟ HIGH (Logic 1) āĻšā§Ÿ, āϤāĻ–āύāχ āφāωāϟāĻĒ⧁āϟ HIGH (Logic 1) āĻšāĻŦ⧇āĨ¤ āĻ•āĻŋāĻ¨ā§āϤ⧁ āϝāĻ–āύ āωāϭ⧟ āχāύāĻĒ⧁āϟ HIGH (Logic 1) āĻ…āĻĨāĻŦāĻž āωāϭ⧟ āχāύāĻĒ⧁āϟ LOW (Logic 0), āϤāĻ–āύ XOR gate-āĻāϰ āφāωāϟāĻĒ⧁āϟ LOW (Logic 0) āĻšāĻŦ⧇āĨ¤ Figure-1 āĻ XOR gate-āĻāϰ āϞāϜāĻŋāĻ• āϏāĻŋāĻŽā§āĻŦāϞ āĻĻ⧇āĻ–āĻžāύ⧋ āĻšā§Ÿā§‡āϛ⧇āĨ¤

Implementation of XOR Gate From NAND Gate 1Âļ

āϏ⧁āϤāϰāĻžāĻ‚, XOR gate āĻļ⧁āϧ⧁āĻŽāĻžāĻ¤ā§āϰ āϤāĻ–āύāχ HIGH āφāωāϟāĻĒ⧁āϟ āĻĻā§‡ā§Ÿ āϝāĻ–āύ āĻāϰ āχāύāĻĒ⧁āϟāϗ⧁āϞ⧋ āϏāĻŽāĻžāύ āύāĻž āĻšā§ŸāĨ¤ āĻāϜāĻ¨ā§āϝ XOR gate-āϕ⧇ "anti-coincidence gate" āĻŦāĻž "inequality detector" āĻ“ āĻŦāϞāĻž āĻšā§ŸāĨ¤

Output Equation of XOR GateÂļ

XOR gate-āĻāϰ āφāωāϟāĻĒ⧁āϟ āĻšāϞ⧋ āχāύāĻĒ⧁āĻŸā§‡āϰ modulo sum, āĻ…āĻ°ā§āĻĨāĻžā§Ž

\[ Y = A \oplus B = A\overline{B} + \overline{A}B \]

āĻāĻ–āĻžāύ⧇, A āĻāĻŦāĻ‚ B āĻšāϞ⧋ XOR gate-āĻāϰ āĻĻ⧁āϟāĻŋ āχāύāĻĒ⧁āϟ āĻ­ā§āϝāĻžāϰāĻŋā§Ÿā§‡āĻŦāϞ, āφāϰ Y āĻšāϞ⧋ āφāωāϟāĻĒ⧁āϟ āĻ­ā§āϝāĻžāϰāĻŋā§Ÿā§‡āĻŦāϞāĨ¤ āφāωāϟāĻĒ⧁āϟ āϏāĻŽā§€āĻ•āϰāĻŖāϟāĻŋ āĻĒ⧜āĻž āϝāĻžā§Ÿ āĻāĻ­āĻžāĻŦ⧇: Y = A ex-or BāĨ¤

Truth Table of XOR GateÂļ

āύāĻŋāĻšā§‡ XOR gate-āĻāϰ truth table āĻĻ⧇āĻ“ā§ŸāĻž āĻšāϞ⧋ āϝ⧇āĻ–āĻžāύ⧇ āχāύāĻĒ⧁āϟ āĻ“ āφāωāϟāĻĒ⧁āĻŸā§‡āϰ āϏāĻŽā§āĻĒāĻ°ā§āĻ• āĻĻ⧇āĻ–āĻžāύ⧋ āĻšā§Ÿā§‡āϛ⧇āĨ¤

A B Output (Y = A¡BĖ… + AĖ…ÂˇB)
0 0 0
0 1 1
1 0 1
1 1 0

What is a NAND Gate?Âļ

NAND Gate āĻšāϞ⧋ āĻāĻ• āϧāϰāύ⧇āϰ universal logic gate, āϝ⧇āϟāĻŋ āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻ•āϰ⧇ āϝ⧇āϕ⧋āύ⧋ āϧāϰāύ⧇āϰ āϞāϜāĻŋāĻ•ā§āϝāĻžāϞ āĻāĻ•ā§āϏāĻĒā§āϰ⧇āĻļāύ āĻŦāĻž āĻ…āĻ¨ā§āϝ āϝ⧇āϕ⧋āύ⧋ logic gate āĻŦāĻžāĻ¸ā§āϤāĻŦāĻžā§Ÿāύ āĻ•āϰāĻž āϝāĻžā§ŸāĨ¤ āĻāĻ•āϟāĻŋ NAND gate āĻŽā§‚āϞāϤ AND gate āĻāĻŦāĻ‚ NOT gate-āĻāϰ āϏāĻŽāĻ¨ā§āĻŦ⧟āĨ¤ āĻ…āĻ°ā§āĻĨāĻžā§Ž,

\[ \text{NAND Logic} = \text{AND Logic} + \text{NOT Logic} \]

NAND gate-āĻāϰ āφāωāϟāĻĒ⧁āϟ LOW (Logic 0) āĻšāĻŦ⧇ āĻļ⧁āϧ⧁āĻŽāĻžāĻ¤ā§āϰ āϤāĻ–āύāχ āϝāĻ–āύ āϏāĻŦ āχāύāĻĒ⧁āϟ HIGH āĻĨāĻžāĻ•āĻŦ⧇āĨ¤ āĻ…āĻ¨ā§āϝ āϝ⧇āϕ⧋āύ⧋ āĻ…āĻŦāĻ¸ā§āĻĨāĻžā§Ÿ āĻāϰ āφāωāϟāĻĒ⧁āϟ HIGH (Logic 1) āĻšāĻŦ⧇āĨ¤ āϤāĻžāχ NAND gate-āĻāϰ āĻ•āĻžāĻ°ā§āϝāĻĒā§āϰāĻŖāĻžāϞ⧀ AND gate-āĻāϰ āωāĻ˛ā§āĻŸā§‹āĨ¤ Figure-2 āϤ⧇ āĻāĻ•āϟāĻŋ two-input NAND gate-āĻāϰ āϞāϜāĻŋāĻ• āϏāĻŋāĻŽā§āĻŦāϞ āĻĻ⧇āĻ–āĻžāύ⧋ āĻšā§Ÿā§‡āϛ⧇āĨ¤

Implementation of XOR Gate From NAND Gate 2Âļ

Output Equation of NAND GateÂļ

āϝāĻĻāĻŋ A āĻāĻŦāĻ‚ B āχāύāĻĒ⧁āϟ āĻ­ā§āϝāĻžāϰāĻŋā§Ÿā§‡āĻŦāϞ āĻšā§Ÿ āĻāĻŦāĻ‚ Y āφāωāϟāĻĒ⧁āϟ āĻ­ā§āϝāĻžāϰāĻŋā§Ÿā§‡āĻŦāϞ āĻšā§Ÿ, āϤāĻžāĻšāϞ⧇ āφāωāϟāĻĒ⧁āϟ āĻšāĻŦ⧇:

\[ Y = \overline{(A \cdot B)} \]

āĻāϟāĻŋ āĻĒ⧜āĻž āϝāĻžā§Ÿ: Y = A¡B whole barāĨ¤

Truth Table of NAND GateÂļ

āύāĻŋāĻšā§‡ NAND gate-āĻāϰ truth table āĻĻ⧇āĻ–āĻžāύ⧋ āĻšāϞ⧋:

A B Output (\(Y = \overline{(A \cdot B)}\))
0 0 1
0 1 1
1 0 1
1 1 0

Implementation of XOR Gate from NAND GateÂļ

āωāĻĒāϰ⧇ āϝ⧇āĻŽāύ āφāϞ⧋āϚāύāĻž āĻ•āϰāĻž āĻšā§Ÿā§‡āϛ⧇, NAND gate āĻāĻ•āϟāĻŋ universal logicāĨ¤ āĻ…āĻ°ā§āĻĨāĻžā§Ž āĻāϟāĻŋ āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻ•āϰ⧇ āĻ…āĻ¨ā§āϝ āϝ⧇āϕ⧋āύ⧋ logic gate āϤ⧈āϰāĻŋ āĻ•āϰāĻž āϏāĻŽā§āĻ­āĻŦāĨ¤ Figure-3 āϤ⧇ āĻĻ⧇āĻ–āĻžāύ⧋ āĻšā§Ÿā§‡āϛ⧇ āϕ⧀āĻ­āĻžāĻŦ⧇ āĻļ⧁āϧ⧁āĻŽāĻžāĻ¤ā§āϰ NAND gate āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻ•āϰ⧇ āĻāĻ•āϟāĻŋ XOR gate āĻŦāĻžāĻ¸ā§āϤāĻŦāĻžā§Ÿāύ āĻ•āϰāĻž āϝāĻžā§ŸāĨ¤

Implementation of XOR Gate From NAND Gate 3Âļ

Logic circuit diagram āĻĨ⧇āϕ⧇ āĻĻ⧇āĻ–āĻž āϝāĻžāĻšā§āϛ⧇ XOR gate āϤ⧈āϰāĻŋ āĻ•āϰāϤ⧇ āĻŽā§‹āϟ ā§ĒāϟāĻŋ NAND gate āĻĒā§āĻ°ā§Ÿā§‹āϜāύāĨ¤

āĻāĻ–āύ āĻĻ⧇āĻ–āĻŋ āĻāχ NAND logic circuit āϕ⧀āĻ­āĻžāĻŦ⧇ āĻ•āĻžāϜ āĻ•āϰ⧇ āĻāĻŦāĻ‚ XOR gate-āĻāϰ āϏāĻŽāĻžāύ āφāωāϟāĻĒ⧁āϟ āĻĻā§‡ā§ŸāĨ¤

āĻĒā§āϰāĻĨāĻŽ NAND gate-āĻāϰ āφāωāϟāĻĒ⧁āϟ:

\[ Y_1 = \overline{(A \cdot B)} \]

āĻĻā§āĻŦāĻŋāĻ¤ā§€ā§Ÿ āĻāĻŦāĻ‚ āϤ⧃āĻ¤ā§€ā§Ÿ NAND gate-āĻāϰ āφāωāϟāĻĒ⧁āϟ:

\[ Y_2 = \overline{(A \cdot Y_1)} = \overline{(A \cdot \overline{(A \cdot B)})} \]
\[ Y_3 = \overline{(B \cdot Y_1)} = \overline{(B \cdot \overline{(A \cdot B)})} \]

āĻļ⧇āώ⧇, āĻāχ āĻĻ⧁āχāϟāĻŋ āφāωāϟāĻĒ⧁āϟ (Y2 āĻāĻŦāĻ‚ Y3) āϚāϤ⧁āĻ°ā§āĻĨ NAND gate-āĻ āĻĻ⧇āĻ“ā§ŸāĻž āĻšāϞ⧇ āφāωāϟāĻĒ⧁āϟ āĻšāĻŦ⧇:

\[ Y = \overline{(Y_2 \cdot Y_3)} \]

⇒ $$ Y = A\overline{B} + \overline{A}B $$

⇒ $$ Y = A \oplus B $$

āφāϰ⧇āĻ•āϟ⧁ details āĻ

  1. XOR Gate Expression:
\[ Y = \overline{A}B + A\overline{B} \]
  1. Double complement form:
\[ \big[\,( \overline{A}B + A\overline{B} )'\,\big]' \]
  1. Internal complement:
\[ \big[\,(\overline{A}B)' \cdot (A\overline{B})'\,\big]' \]
  1. Final NAND form (De-Morgan’s Law):
\[ Y = \big((\overline{A}B)' \cdot (A\overline{B})'\big)' \;=\; \overline{A}B + A\overline{B} \]

Implementation of XOR Gate from NAND Gate

XOR using NAND Gate
āĻāϟāĻžāχ āĻšāϞ⧋ XOR gate-āĻāϰ āφāωāϟāĻĒ⧁āϟāĨ¤ āϏ⧁āϤāϰāĻžāĻ‚, āĻļ⧁āϧ⧁āĻŽāĻžāĻ¤ā§āϰ NAND gate āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻ•āϰ⧇āĻ“ XOR gate āĻŦāĻžāĻ¸ā§āϤāĻŦāĻžā§Ÿāύ āĻ•āϰāĻž āϏāĻŽā§āĻ­āĻŦāĨ¤

✅ XNOR Gate Using NAND GateÂļ

XNOR

  • āϧāĻžāĻĒ⧇ āϧāĻžāĻĒ⧇ NAND āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻ•āϰ⧇ āφāωāϟāĻĒ⧁āϟ = \(\overline{A \oplus B}\) |
  • āĻšā§‚ā§œāĻžāĻ¨ā§āϤ āφāωāϟāĻĒ⧁āϟ = XNOR Gate |

image-47.png

Full AND/OR/NOT Set to Implement Ex-NORÂļ

What is a XNOR Gate?Âļ

XNOR (Exclusive-NOR) Gate āĻšāϞ⧋ āĻāĻ• āϧāϰāύ⧇āϰ derived logic gateāĨ¤ XNOR gate-āĻāϰ āĻĻ⧁āϟāĻŋ āχāύāĻĒ⧁āϟ āĻāĻŦāĻ‚ āĻāĻ•āϟāĻŋ āφāωāϟāĻĒ⧁āϟ āĻĨāĻžāϕ⧇āĨ¤ āϝāĻ–āύ āĻĻ⧁āϟāĻŋ āχāύāĻĒ⧁āϟ āϏāĻŽāĻžāύ āĻšā§Ÿ (āωāϭ⧟āχ HIGH āĻŦāĻž āωāϭ⧟āχ LOW), āϤāĻ–āύ āφāωāϟāĻĒ⧁āϟ HIGH (Logic 1) āĻšā§ŸāĨ¤ āφāϰ āχāύāĻĒ⧁āϟ āφāϞāĻžāĻĻāĻž āĻšāϞ⧇ āφāωāϟāĻĒ⧁āϟ LOW (Logic 0) āĻšā§ŸāĨ¤ Figure-1 āĻ XNOR gate-āĻāϰ āϞāϜāĻŋāĻ• āϏāĻŋāĻŽā§āĻŦāϞ āĻĻ⧇āĻ–āĻžāύ⧋ āĻšā§Ÿā§‡āϛ⧇āĨ¤

Output Equation of XNOR GateÂļ

\[ Y = \overline{(A \oplus B)} = AB + \overline{A}\,\overline{B} \]

Truth Table of XNOR GateÂļ

A B Output (\(Y = \overline{(A \oplus B)}\))
0 0 1
0 1 0
1 0 0
1 1 1

What is a NAND Gate?Âļ

NAND Gate āĻšāϞ⧋ āĻāĻ• āϧāϰāύ⧇āϰ universal logic gateāĨ¤ āĻāϟāĻŋ āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻ•āϰ⧇ āϝ⧇āϕ⧋āύ⧋ logic gate āϤ⧈āϰāĻŋ āĻ•āϰāĻž āϝāĻžā§ŸāĨ¤ NAND gate āĻŽā§‚āϞāϤ AND + NOT āĻāϰ āϏāĻŽāĻ¨ā§āĻŦ⧟āĨ¤

Output Equation of NAND GateÂļ

\[ Y = \overline{(A \cdot B)} \]

Truth Table of NAND GateÂļ

A B Output (\(Y = \overline{(A \cdot B)}\))
0 0 1
0 1 1
1 0 1
1 1 0

Implementation of XNOR Gate from NAND GateÂļ

NAND gate āĻāĻ•āϟāĻŋ universal logic gate, āϤāĻžāχ āĻāϟāĻŋ āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻ•āϰ⧇ XNOR gate āϤ⧈āϰāĻŋ āĻ•āϰāĻž āϝāĻžā§ŸāĨ¤ āύāĻŋāĻšā§‡āϰ āϞāϜāĻŋāĻ• āϏāĻžāĻ°ā§āĻ•āĻŋāĻŸā§‡ ā§ĢāϟāĻŋ NAND gate āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻ•āϰ⧇ āĻāĻ•āϟāĻŋ XNOR gate āĻŦāĻžāĻ¸ā§āϤāĻŦāĻžā§Ÿāύ āĻĻ⧇āĻ–āĻžāύ⧋ āĻšā§Ÿā§‡āϛ⧇ (Figure-3)āĨ¤

āϧāĻžāĻĒ⧇ āϧāĻžāĻĒ⧇ āφāωāϟāĻĒ⧁āϟ āύāĻŋāĻ°ā§āϪ⧟Âļ

āĻĒā§āϰāĻĨāĻŽ NAND gate-āĻāϰ āφāωāϟāĻĒ⧁āϟ:

\[ Y_1 = \overline{(A \cdot B)} \]

āĻĻā§āĻŦāĻŋāĻ¤ā§€ā§Ÿ NAND gate-āĻāϰ āφāωāϟāĻĒ⧁āϟ:

\[ Y_2 = \overline{(A \cdot Y_1)} = \overline{(A \cdot \overline{(A \cdot B)})} \]

āϤ⧃āĻ¤ā§€ā§Ÿ NAND gate-āĻāϰ āφāωāϟāĻĒ⧁āϟ:

\[ Y_3 = \overline{(B \cdot Y_1)} = \overline{(B \cdot \overline{(A \cdot B)})} \]

āϚāϤ⧁āĻ°ā§āĻĨ NAND gate-āĻāϰ āφāωāϟāĻĒ⧁āϟ:

\[ Y_4 = \overline{(Y_2 \cdot Y_3)} \]

āĻļ⧇āώ⧇, āĻĒāĻžā§āϚāĻŽ NAND gate-āĻ $Y_1$ āĻāĻŦāĻ‚ $Y_4$ āĻĻāĻŋāϞ⧇ āĻĒāĻžāĻ“ā§ŸāĻž āϝāĻžā§Ÿ:

\[ Y = \overline{(Y_1 \cdot Y_4)} \]

āĻāĻ–āύ expand āĻ•āϰāϞ⧇:

⇒ \(Y = AB + \overline{A}\,\overline{B}\)
⇒ \(Y = \overline{(A \oplus B)}\)


✅ āĻāχāĻ­āĻžāĻŦ⧇āχ āĻļ⧁āϧ⧁āĻŽāĻžāĻ¤ā§āϰ NAND gate āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻ•āϰ⧇ XNOR gate āϤ⧈āϰāĻŋ āĻ•āϰāĻž āϏāĻŽā§āĻ­āĻŦāĨ¤

Try yourself:Âļ


Universal Logic Gates using only NAND GatesÂļ

Universal Logic Gates using only NAND GatesÂļ

đŸŸĨ NOR Universal Logic GateÂļ

✅ AND Gate Using NOR GateÂļ

  • āĻĻāϰāĻ•āĻžāϰ āĻšāĻŦ⧇ 3āϟāĻž NOR gate |
  • 1āĻŽ NOR Gate → āφāωāϟāĻĒ⧁āϟ = \(\overline{A + B}\) |
  • 2⧟ NOR Gate → āφāωāϟāĻĒ⧁āϟ = \(\overline{\overline{A + B}} = A + B\) |
  • 3⧟ NOR Gate → āφāωāϟāĻĒ⧁āϟ = \(\overline{(A + B)} = A \cdot B\) (De Morgan’s Law) |
  • āĻšā§‚ā§œāĻžāĻ¨ā§āϤ āφāωāϟāĻĒ⧁āϟ = AND Gate |

✅ OR Gate Using NOR GateÂļ

  • āĻĻāϰāĻ•āĻžāϰ āĻšāĻŦ⧇ 2āϟāĻž NOR gate |
  • 1āĻŽ NOR Gate → āφāωāϟāĻĒ⧁āϟ = \(\overline{A}\), \(\overline{B}\) |
  • 2⧟ NOR Gate → āφāωāϟāĻĒ⧁āϟ = \(\overline{\overline{A} + \overline{B}} = A + B\) |
  • āĻšā§‚ā§œāĻžāĻ¨ā§āϤ āφāωāϟāĻĒ⧁āϟ = OR Gate |

✅ NAND Gate Using NOR GateÂļ

  • āĻĻāϰāĻ•āĻžāϰ āĻšāĻŦ⧇ 3āϟāĻž NOR gate |
  • 1āĻŽ NOR Gate → āφāωāϟāĻĒ⧁āϟ = \(\overline{A}\) |
  • 2⧟ NOR Gate → āφāωāϟāĻĒ⧁āϟ = \(\overline{B}\) |
  • 3⧟ NOR Gate → āφāωāϟāĻĒ⧁āϟ = \(\overline{\overline{A} + \overline{B}} = A \cdot B\) |
  • āĻšā§‚ā§œāĻžāĻ¨ā§āϤ āφāωāϟāĻĒ⧁āϟ = NAND Gate |

✅ XNOR Gate Using NOR GateÂļ

  • āϧāĻžāĻĒ⧇ āϧāĻžāĻĒ⧇ NOR āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻ•āϰ⧇ āφāωāϟāĻĒ⧁āϟ = \(\overline{A \oplus B}\) |
  • āĻšā§‚ā§œāĻžāĻ¨ā§āϤ āφāωāϟāĻĒ⧁āϟ = XNOR Gate |

✅ XOR Gate Using NOR GateÂļ

  • āĻĻāϰāĻ•āĻžāϰ āĻšāĻŦ⧇ 3āϟāĻž NOR gate |
  • āϧāĻžāĻĒ⧇ āϧāĻžāĻĒ⧇ āĻļ⧇āώ⧇ āφāωāϟāĻĒ⧁āϟ = \(A \oplus B\) |
  • āĻšā§‚ā§œāĻžāĻ¨ā§āϤ āφāωāϟāĻĒ⧁āϟ = XOR Gate |

Universal Logic Gates using only NOR GatesÂļ

Universal Logic Gates using only NOR GatesÂļ

📌 Final Note:
👉 āĻļ⧁āϧ⧁ NAND Gate āĻ…āĻĨāĻŦāĻž āĻļ⧁āϧ⧁ NOR Gate āĻĻāĻŋā§Ÿā§‡āχ āĻ…āĻ¨ā§āϝ āϏāĻŦ Logic Gate āϤ⧈āϰāĻŋ āĻ•āϰāĻž āϝāĻžā§Ÿ | āĻāϜāĻ¨ā§āϝ āĻāϗ⧁āϞ⧋āϕ⧇ āĻŦāϞāĻž āĻšā§Ÿ Universal Logic Gate |