Universal Gate implementationÂļ
đ Universal Logic GatesÂļ
āĻĄāĻŋāĻāĻŋāĻāĻžāϞ āϏāĻžāϰā§āĻāĻŋāĻā§ NAND Gate āĻāϰ NOR Gate āĻā§ āĻŦāϞāĻž āĻšā§ Universal Logic GateāĨ¤
đ āĻāĻžāϰāĻŖ āĻļā§āϧ⧠āĻāĻ āĻĻā§āĻ āϧāϰāύā§āϰ Gate āĻĻāĻŋā§ā§āĻ āϏāĻŦ Basic Logic Gate (AND, OR, NOT, XOR, XNOR) āϤā§āϰāĻŋ āĻāϰāĻž āϏāĻŽā§āĻāĻŦāĨ¤
đŠ NAND Universal Logic GateÂļ
Explanation of NAND
NAND āĻā§āĻ āĻā§?Âļ
NAND āĻā§āĻ āĻšāϞ⧠āĻāĻ āϧāϰāύā§āϰ Universal Logic GateāĨ¤ āĻāĻāĻžāϰ āĻĻā§āĻ āĻŦāĻž āϤāĻžāϰ āĻŦā§āĻļāĻŋ āĻāύāĻĒā§āĻ āĻĨāĻžāĻāϤ⧠āĻĒāĻžāϰ⧠āĻāĻŦāĻ āĻāĻāĻāĻĒā§āĻ āĻĨāĻžāĻā§ āϏāĻŦāϏāĻŽā§ āĻāĻāĻāĻŋāĻāĨ¤
đ āϝāĻāύ āϏāĻŦ āĻāύāĻĒā§āĻ = 1, āϤāĻāύ āĻāĻāĻāĻĒā§āĻ āĻšāĻŦā§ 0āĨ¤
đ āĻ
āύā§āϝ āϝā§āĻā§āύ⧠āĻāύāĻĒā§āĻ āĻāĻŽā§āĻŦāĻŋāύā§āĻļāύ⧠āĻāĻāĻāĻĒā§āĻ āĻšāĻŦā§ 1āĨ¤

NAND āĻā§āĻā§āϰ āĻĒā§āϰāϤā§āĻ (Symbol)
āĻĻā§āĻ āĻāύāĻĒā§āĻ NAND āĻā§āĻā§āϰ Truth Table āύāĻŋāĻā§ āĻĻā§āĻā§āĻž āĻšāϞā§:
| āĻāύāĻĒā§āĻ A | āĻāύāĻĒā§āĻ B | āĻāĻāĻāĻĒā§āĻ Y |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Boolean Function:
āĻāĻāĻžāύ⧠\(AB\)-āĻāϰ āĻāĻĒāϰ āĻŦāĻžāϰ āĻāĻŋāĻšā§āύāĻāĻŋ āύāĻŋāϰā§āĻĻā§āĻļ āĻāϰāĻā§ AND āĻāϰ āĻāϞā§āĻā§ āĻŽāĻžāύ āĻŦāĻž NOT operationāĨ¤
NAND gate as NOT
NAND āĻā§āĻ āĻĻāĻŋā§ā§ NOT āĻā§āĻ āϤā§āϰāĻŋ:Âļ
āĻāĻāύ āĻĻā§āĻāĻž āϝāĻžāĻ, āĻāĻŋāĻāĻžāĻŦā§ āĻļā§āϧ⧠NAND āĻā§āĻ āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻāϰ⧠NOT Gate āĻŦāĻžāύāĻžāύ⧠āϝāĻžā§āĨ¤
NOT āĻā§āĻā§āϰ āĻāĻāĻāĻĒā§āĻ āĻĢāĻžāĻāĻļāύ āĻšāϞā§:
āĻ āύā§āϝāĻĻāĻŋāĻā§, NAND āĻā§āĻā§āϰ āĻāĻāĻāĻĒā§āĻ āĻšāϞā§:
đ āϝāĻĻāĻŋ āĻāĻŽāϰāĻž NAND āĻā§āĻā§āϰ āĻĻā§āĻ āĻāύāĻĒā§āĻāĻā§ āĻāĻāĻ āϏāĻŋāĻāύā§āϝāĻžāϞ āĻĻāĻŋāĻ, āĻ āϰā§āĻĨāĻžā§ \(A = B = A\), āϤāĻžāĻšāϞā§:
āĻāĻāĻžāĻ āĻšāĻā§āĻā§ NOT Gate-āĻāϰ āϏāĻŽāĻžāύ āĻāĻāĻāĻĒā§āĻāĨ¤
Circuit DiagramÂļ
NOT āĻā§āĻ NAND āĻā§āĻ āĻĻāĻŋā§ā§ āĻŦāĻžāύāĻžāϤ⧠āĻšāϞā§:

* āĻāĻā§ āĻāύāĻĒā§āĻāĻā§ āĻāĻāϏāĻžāĻĨā§ āĻļāϰā§āĻ āĻāϰ⧠āĻāĻāĻ āĻāύāĻĒā§āĻ āĻĻāĻŋāϤ⧠āĻšāĻŦā§āĨ¤
* āĻāĻāĻāĻĒā§āĻ āϞāĻžāĻāύ⧠āĻĒāĻžāĻā§āĻž āϝāĻžāĻŦā§ āĻāϞā§āĻāĻžāύ⧠āĻŽāĻžāύ (Inverter Output)āĨ¤
āĻ āύā§āϝāĻāĻžāĻŦā§, āϝāĻĻāĻŋ āĻāĻ āĻāύāĻĒā§āĻāĻā§ Logic 1 āĻĻā§āĻā§āĻž āĻšā§ āĻāĻŦāĻ āĻ āύā§āϝ āĻāύāĻĒā§āĻā§ \(A\) āĻĻā§āĻā§āĻž āĻšā§, āϤāĻžāĻšāϞā§āĻ āĻāĻāĻāĻĒā§āĻ āĻšāĻŦā§:
ConclusionÂļ
āĻāĻŽāϰāĻž āĻĻā§āĻāϞāĻžāĻŽ āĻā§āĻāĻžāĻŦā§ āĻāĻāĻāĻŋ NAND Gate āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻāϰ⧠NOT Gate āϤā§āϰāĻŋ āĻāϰāĻž āϝāĻžā§āĨ¤ āϏāĻžāϰā§āĻāĻŋāĻ āĻĄāĻžā§āĻžāĻā§āϰāĻžāĻŽā§āϰ āϏāĻžāĻšāĻžāϝā§āϝ⧠āĻŦāĻŋāώā§āĻāĻŋ āĻāϰāĻ āĻĒāϰāĻŋāώā§āĻāĻžāϰ āĻšā§ā§āĻā§āĨ¤
â AND Gate Using NAND GateÂļ
- āĻĻāϰāĻāĻžāϰ āĻšāĻŦā§ 2āĻāĻž NAND gate |
- 1āĻŽ NAND Gate â āĻāĻāĻāĻĒā§āĻ = \(\overline{A \cdot B}\) |
- 2ā§ NAND Gate â āĻāĻāĻāĻĒā§āĻ = \(\overline{\overline{A \cdot B}} = A \cdot B\) |
- āĻā§ā§āĻžāύā§āϤ āĻāĻāĻāĻĒā§āĻ = AND Gate |
Âļ
â OR Gate Using NAND GateÂļ
((AA)'(BB)')'= (A'B')' (By Idempotent Law)
= A''+B'' (By De Morganâs Law)
= A+B ( By involution Law)
- āĻĻāϰāĻāĻžāϰ āĻšāĻŦā§ 3āĻāĻž NAND gate |
- 1āĻŽ NAND Gate â āĻāĻāĻāĻĒā§āĻ = \(\overline{A}\) |
- 2ā§ NAND Gate â āĻāĻāĻāĻĒā§āĻ = \(\overline{B}\) |
- 3ā§ NAND Gate â āĻāĻāĻāĻĒā§āĻ = \(\overline{\overline{A} \cdot \overline{B}} = A + B\) |
- āĻā§ā§āĻžāύā§āϤ āĻāĻāĻāĻĒā§āĻ = OR Gate |
Âļ
â NOR Gate Using NAND GateÂļ
- āĻĻāϰāĻāĻžāϰ āĻšāĻŦā§ 3āĻāĻž NAND gate |
- 1āĻŽ NAND Gate â āĻāĻāĻāĻĒā§āĻ = \(\overline{A \cdot B}\) |
- 2ā§ NAND Gate â āĻāĻāĻāĻĒā§āĻ = \(\overline{\overline{A \cdot B}} = A \cdot B\) |
- 3ā§ NAND Gate â āĻāĻāĻāĻĒā§āĻ = \(\overline{(A \cdot B) \cdot (A \cdot B)} = \overline{A \cdot B}\) |
- āĻā§ā§āĻžāύā§āϤ āĻāĻāĻāĻĒā§āĻ = NOR Gate |
XOR Gate Using NAND Gate
- āĻĻāϰāĻāĻžāϰ āĻšāĻŦā§ 4āĻāĻž NAND gate.
- āϧāĻžāĻĒā§ āϧāĻžāĻĒā§ āĻļā§āώ⧠āĻāĻāĻāĻĒā§āĻ = \(A \oplus B\) .
- āĻā§ā§āĻžāύā§āϤ āĻāĻāĻāĻĒā§āĻ = XOR Gate.
What is a XOR Gate?Âļ
XOR (Exclusive-OR) Gate āĻšāϞ⧠āĻāĻ āϧāϰāύā§āϰ derived logic gateāĨ¤ XOR gate-āĻāϰ āĻĻā§āĻāĻŋ āĻāύāĻĒā§āĻ āĻāĻŦāĻ āĻāĻāĻāĻŋ āĻāĻāĻāĻĒā§āĻ āĻĨāĻžāĻā§āĨ¤ āϝāĻāύ āĻĻā§āĻāĻŋ āĻāύāĻĒā§āĻā§āϰ āĻŽāϧā§āϝ⧠āĻāĻāĻāĻŋāĻŽāĻžāϤā§āϰ āĻāύāĻĒā§āĻ HIGH (Logic 1) āĻšā§, āϤāĻāύāĻ āĻāĻāĻāĻĒā§āĻ HIGH (Logic 1) āĻšāĻŦā§āĨ¤ āĻāĻŋāύā§āϤ⧠āϝāĻāύ āĻāĻā§ āĻāύāĻĒā§āĻ HIGH (Logic 1) āĻ āĻĨāĻŦāĻž āĻāĻā§ āĻāύāĻĒā§āĻ LOW (Logic 0), āϤāĻāύ XOR gate-āĻāϰ āĻāĻāĻāĻĒā§āĻ LOW (Logic 0) āĻšāĻŦā§āĨ¤ Figure-1 āĻ XOR gate-āĻāϰ āϞāĻāĻŋāĻ āϏāĻŋāĻŽā§āĻŦāϞ āĻĻā§āĻāĻžāύ⧠āĻšā§ā§āĻā§āĨ¤
Implementation of XOR Gate From NAND Gate 1Âļ
āϏā§āϤāϰāĻžāĻ, XOR gate āĻļā§āϧā§āĻŽāĻžāϤā§āϰ āϤāĻāύāĻ HIGH āĻāĻāĻāĻĒā§āĻ āĻĻā§ā§ āϝāĻāύ āĻāϰ āĻāύāĻĒā§āĻāĻā§āϞ⧠āϏāĻŽāĻžāύ āύāĻž āĻšā§āĨ¤ āĻāĻāύā§āϝ XOR gate-āĻā§ "anti-coincidence gate" āĻŦāĻž "inequality detector" āĻ āĻŦāϞāĻž āĻšā§āĨ¤
Output Equation of XOR GateÂļ
XOR gate-āĻāϰ āĻāĻāĻāĻĒā§āĻ āĻšāϞ⧠āĻāύāĻĒā§āĻā§āϰ modulo sum, āĻ āϰā§āĻĨāĻžā§
āĻāĻāĻžāύā§, A āĻāĻŦāĻ B āĻšāϞ⧠XOR gate-āĻāϰ āĻĻā§āĻāĻŋ āĻāύāĻĒā§āĻ āĻā§āϝāĻžāϰāĻŋā§ā§āĻŦāϞ, āĻāϰ Y āĻšāϞ⧠āĻāĻāĻāĻĒā§āĻ āĻā§āϝāĻžāϰāĻŋā§ā§āĻŦāϞāĨ¤ āĻāĻāĻāĻĒā§āĻ āϏāĻŽā§āĻāϰāĻŖāĻāĻŋ āĻĒā§āĻž āϝāĻžā§ āĻāĻāĻžāĻŦā§: Y = A ex-or BāĨ¤
Truth Table of XOR GateÂļ
āύāĻŋāĻā§ XOR gate-āĻāϰ truth table āĻĻā§āĻā§āĻž āĻšāϞ⧠āϝā§āĻāĻžāύ⧠āĻāύāĻĒā§āĻ āĻ āĻāĻāĻāĻĒā§āĻā§āϰ āϏāĻŽā§āĻĒāϰā§āĻ āĻĻā§āĻāĻžāύ⧠āĻšā§ā§āĻā§āĨ¤
| A | B | Output (Y = A¡BĖ + AĖ ÂˇB) |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
What is a NAND Gate?Âļ
NAND Gate āĻšāϞ⧠āĻāĻ āϧāϰāύā§āϰ universal logic gate, āϝā§āĻāĻŋ āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻāϰ⧠āϝā§āĻā§āύ⧠āϧāϰāύā§āϰ āϞāĻāĻŋāĻā§āϝāĻžāϞ āĻāĻā§āϏāĻĒā§āϰā§āĻļāύ āĻŦāĻž āĻ āύā§āϝ āϝā§āĻā§āύ⧠logic gate āĻŦāĻžāϏā§āϤāĻŦāĻžā§āύ āĻāϰāĻž āϝāĻžā§āĨ¤ āĻāĻāĻāĻŋ NAND gate āĻŽā§āϞāϤ AND gate āĻāĻŦāĻ NOT gate-āĻāϰ āϏāĻŽāύā§āĻŦā§āĨ¤ āĻ āϰā§āĻĨāĻžā§,
NAND gate-āĻāϰ āĻāĻāĻāĻĒā§āĻ LOW (Logic 0) āĻšāĻŦā§ āĻļā§āϧā§āĻŽāĻžāϤā§āϰ āϤāĻāύāĻ āϝāĻāύ āϏāĻŦ āĻāύāĻĒā§āĻ HIGH āĻĨāĻžāĻāĻŦā§āĨ¤ āĻ āύā§āϝ āϝā§āĻā§āύ⧠āĻ āĻŦāϏā§āĻĨāĻžā§ āĻāϰ āĻāĻāĻāĻĒā§āĻ HIGH (Logic 1) āĻšāĻŦā§āĨ¤ āϤāĻžāĻ NAND gate-āĻāϰ āĻāĻžāϰā§āϝāĻĒā§āϰāĻŖāĻžāϞ⧠AND gate-āĻāϰ āĻāϞā§āĻā§āĨ¤ Figure-2 āϤ⧠āĻāĻāĻāĻŋ two-input NAND gate-āĻāϰ āϞāĻāĻŋāĻ āϏāĻŋāĻŽā§āĻŦāϞ āĻĻā§āĻāĻžāύ⧠āĻšā§ā§āĻā§āĨ¤
Implementation of XOR Gate From NAND Gate 2Âļ
Output Equation of NAND GateÂļ
āϝāĻĻāĻŋ A āĻāĻŦāĻ B āĻāύāĻĒā§āĻ āĻā§āϝāĻžāϰāĻŋā§ā§āĻŦāϞ āĻšā§ āĻāĻŦāĻ Y āĻāĻāĻāĻĒā§āĻ āĻā§āϝāĻžāϰāĻŋā§ā§āĻŦāϞ āĻšā§, āϤāĻžāĻšāϞ⧠āĻāĻāĻāĻĒā§āĻ āĻšāĻŦā§:
āĻāĻāĻŋ āĻĒā§āĻž āϝāĻžā§: Y = A¡B whole barāĨ¤
Truth Table of NAND GateÂļ
āύāĻŋāĻā§ NAND gate-āĻāϰ truth table āĻĻā§āĻāĻžāύ⧠āĻšāϞā§:
| A | B | Output (\(Y = \overline{(A \cdot B)}\)) |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Implementation of XOR Gate from NAND GateÂļ
āĻāĻĒāϰ⧠āϝā§āĻŽāύ āĻāϞā§āĻāύāĻž āĻāϰāĻž āĻšā§ā§āĻā§, NAND gate āĻāĻāĻāĻŋ universal logicāĨ¤ āĻ āϰā§āĻĨāĻžā§ āĻāĻāĻŋ āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻāϰ⧠āĻ āύā§āϝ āϝā§āĻā§āύ⧠logic gate āϤā§āϰāĻŋ āĻāϰāĻž āϏāĻŽā§āĻāĻŦāĨ¤ Figure-3 āϤ⧠āĻĻā§āĻāĻžāύ⧠āĻšā§ā§āĻā§ āĻā§āĻāĻžāĻŦā§ āĻļā§āϧā§āĻŽāĻžāϤā§āϰ NAND gate āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻāϰ⧠āĻāĻāĻāĻŋ XOR gate āĻŦāĻžāϏā§āϤāĻŦāĻžā§āύ āĻāϰāĻž āϝāĻžā§āĨ¤
Implementation of XOR Gate From NAND Gate 3Âļ
Logic circuit diagram āĻĨā§āĻā§ āĻĻā§āĻāĻž āϝāĻžāĻā§āĻā§ XOR gate āϤā§āϰāĻŋ āĻāϰāϤ⧠āĻŽā§āĻ ā§ĒāĻāĻŋ NAND gate āĻĒā§āϰā§ā§āĻāύāĨ¤
āĻāĻāύ āĻĻā§āĻāĻŋ āĻāĻ NAND logic circuit āĻā§āĻāĻžāĻŦā§ āĻāĻžāĻ āĻāϰ⧠āĻāĻŦāĻ XOR gate-āĻāϰ āϏāĻŽāĻžāύ āĻāĻāĻāĻĒā§āĻ āĻĻā§ā§āĨ¤
āĻĒā§āϰāĻĨāĻŽ NAND gate-āĻāϰ āĻāĻāĻāĻĒā§āĻ:
āĻĻā§āĻŦāĻŋāϤā§ā§ āĻāĻŦāĻ āϤā§āϤā§ā§ NAND gate-āĻāϰ āĻāĻāĻāĻĒā§āĻ:
āĻļā§āώā§, āĻāĻ āĻĻā§āĻāĻāĻŋ āĻāĻāĻāĻĒā§āĻ (Y2 āĻāĻŦāĻ Y3) āĻāϤā§āϰā§āĻĨ NAND gate-āĻ āĻĻā§āĻā§āĻž āĻšāϞ⧠āĻāĻāĻāĻĒā§āĻ āĻšāĻŦā§:
â $$ Y = A\overline{B} + \overline{A}B $$
â $$ Y = A \oplus B $$
āĻāϰā§āĻāĻā§ details āĻ
- XOR Gate Expression:
- Double complement form:
- Internal complement:
- Final NAND form (De-Morganâs Law):

āĻāĻāĻžāĻ āĻšāϞ⧠XOR gate-āĻāϰ āĻāĻāĻāĻĒā§āĻāĨ¤ āϏā§āϤāϰāĻžāĻ, āĻļā§āϧā§āĻŽāĻžāϤā§āϰ NAND gate āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻāϰā§āĻ XOR gate āĻŦāĻžāϏā§āϤāĻŦāĻžā§āύ āĻāϰāĻž āϏāĻŽā§āĻāĻŦāĨ¤
â XNOR Gate Using NAND GateÂļ
XNOR
- āϧāĻžāĻĒā§ āϧāĻžāĻĒā§ NAND āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻāϰ⧠āĻāĻāĻāĻĒā§āĻ = \(\overline{A \oplus B}\) |
- āĻā§ā§āĻžāύā§āϤ āĻāĻāĻāĻĒā§āĻ = XNOR Gate |
Âļ
What is a XNOR Gate?Âļ
XNOR (Exclusive-NOR) Gate āĻšāϞ⧠āĻāĻ āϧāϰāύā§āϰ derived logic gateāĨ¤ XNOR gate-āĻāϰ āĻĻā§āĻāĻŋ āĻāύāĻĒā§āĻ āĻāĻŦāĻ āĻāĻāĻāĻŋ āĻāĻāĻāĻĒā§āĻ āĻĨāĻžāĻā§āĨ¤ āϝāĻāύ āĻĻā§āĻāĻŋ āĻāύāĻĒā§āĻ āϏāĻŽāĻžāύ āĻšā§ (āĻāĻā§āĻ HIGH āĻŦāĻž āĻāĻā§āĻ LOW), āϤāĻāύ āĻāĻāĻāĻĒā§āĻ HIGH (Logic 1) āĻšā§āĨ¤ āĻāϰ āĻāύāĻĒā§āĻ āĻāϞāĻžāĻĻāĻž āĻšāϞ⧠āĻāĻāĻāĻĒā§āĻ LOW (Logic 0) āĻšā§āĨ¤ Figure-1 āĻ XNOR gate-āĻāϰ āϞāĻāĻŋāĻ āϏāĻŋāĻŽā§āĻŦāϞ āĻĻā§āĻāĻžāύ⧠āĻšā§ā§āĻā§āĨ¤
Output Equation of XNOR GateÂļ
Truth Table of XNOR GateÂļ
| A | B | Output (\(Y = \overline{(A \oplus B)}\)) |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
What is a NAND Gate?Âļ
NAND Gate āĻšāϞ⧠āĻāĻ āϧāϰāύā§āϰ universal logic gateāĨ¤ āĻāĻāĻŋ āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻāϰ⧠āϝā§āĻā§āύ⧠logic gate āϤā§āϰāĻŋ āĻāϰāĻž āϝāĻžā§āĨ¤ NAND gate āĻŽā§āϞāϤ AND + NOT āĻāϰ āϏāĻŽāύā§āĻŦā§āĨ¤
Output Equation of NAND GateÂļ
Truth Table of NAND GateÂļ
| A | B | Output (\(Y = \overline{(A \cdot B)}\)) |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Implementation of XNOR Gate from NAND GateÂļ
NAND gate āĻāĻāĻāĻŋ universal logic gate, āϤāĻžāĻ āĻāĻāĻŋ āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻāϰ⧠XNOR gate āϤā§āϰāĻŋ āĻāϰāĻž āϝāĻžā§āĨ¤ āύāĻŋāĻā§āϰ āϞāĻāĻŋāĻ āϏāĻžāϰā§āĻāĻŋāĻā§ ā§ĢāĻāĻŋ NAND gate āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻāϰ⧠āĻāĻāĻāĻŋ XNOR gate āĻŦāĻžāϏā§āϤāĻŦāĻžā§āύ āĻĻā§āĻāĻžāύ⧠āĻšā§ā§āĻā§ (Figure-3)āĨ¤
āϧāĻžāĻĒā§ āϧāĻžāĻĒā§ āĻāĻāĻāĻĒā§āĻ āύāĻŋāϰā§āĻŖā§Âļ
āĻĒā§āϰāĻĨāĻŽ NAND gate-āĻāϰ āĻāĻāĻāĻĒā§āĻ:
āĻĻā§āĻŦāĻŋāϤā§ā§ NAND gate-āĻāϰ āĻāĻāĻāĻĒā§āĻ:
āϤā§āϤā§ā§ NAND gate-āĻāϰ āĻāĻāĻāĻĒā§āĻ:
āĻāϤā§āϰā§āĻĨ NAND gate-āĻāϰ āĻāĻāĻāĻĒā§āĻ:
āĻļā§āώā§, āĻĒāĻā§āĻāĻŽ NAND gate-āĻ $Y_1$ āĻāĻŦāĻ $Y_4$ āĻĻāĻŋāϞ⧠āĻĒāĻžāĻā§āĻž āϝāĻžā§:
āĻāĻāύ expand āĻāϰāϞā§:
â \(Y = AB + \overline{A}\,\overline{B}\)
â \(Y = \overline{(A \oplus B)}\)
â āĻāĻāĻāĻžāĻŦā§āĻ āĻļā§āϧā§āĻŽāĻžāϤā§āϰ NAND gate āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻāϰ⧠XNOR gate āϤā§āϰāĻŋ āĻāϰāĻž āϏāĻŽā§āĻāĻŦāĨ¤
Try yourself:Âļ
Universal Logic Gates using only NAND GatesÂļ
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đĨ NOR Universal Logic GateÂļ
â AND Gate Using NOR GateÂļ
- āĻĻāϰāĻāĻžāϰ āĻšāĻŦā§ 3āĻāĻž NOR gate |
- 1āĻŽ NOR Gate â āĻāĻāĻāĻĒā§āĻ = \(\overline{A + B}\) |
- 2ā§ NOR Gate â āĻāĻāĻāĻĒā§āĻ = \(\overline{\overline{A + B}} = A + B\) |
- 3ā§ NOR Gate â āĻāĻāĻāĻĒā§āĻ = \(\overline{(A + B)} = A \cdot B\) (De Morganâs Law) |
- āĻā§ā§āĻžāύā§āϤ āĻāĻāĻāĻĒā§āĻ = AND Gate |
â OR Gate Using NOR GateÂļ
- āĻĻāϰāĻāĻžāϰ āĻšāĻŦā§ 2āĻāĻž NOR gate |
- 1āĻŽ NOR Gate â āĻāĻāĻāĻĒā§āĻ = \(\overline{A}\), \(\overline{B}\) |
- 2ā§ NOR Gate â āĻāĻāĻāĻĒā§āĻ = \(\overline{\overline{A} + \overline{B}} = A + B\) |
- āĻā§ā§āĻžāύā§āϤ āĻāĻāĻāĻĒā§āĻ = OR Gate |
â NAND Gate Using NOR GateÂļ
- āĻĻāϰāĻāĻžāϰ āĻšāĻŦā§ 3āĻāĻž NOR gate |
- 1āĻŽ NOR Gate â āĻāĻāĻāĻĒā§āĻ = \(\overline{A}\) |
- 2ā§ NOR Gate â āĻāĻāĻāĻĒā§āĻ = \(\overline{B}\) |
- 3ā§ NOR Gate â āĻāĻāĻāĻĒā§āĻ = \(\overline{\overline{A} + \overline{B}} = A \cdot B\) |
- āĻā§ā§āĻžāύā§āϤ āĻāĻāĻāĻĒā§āĻ = NAND Gate |
â XNOR Gate Using NOR GateÂļ
- āϧāĻžāĻĒā§ āϧāĻžāĻĒā§ NOR āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻāϰ⧠āĻāĻāĻāĻĒā§āĻ = \(\overline{A \oplus B}\) |
- āĻā§ā§āĻžāύā§āϤ āĻāĻāĻāĻĒā§āĻ = XNOR Gate |
â XOR Gate Using NOR GateÂļ
- āĻĻāϰāĻāĻžāϰ āĻšāĻŦā§ 3āĻāĻž NOR gate |
- āϧāĻžāĻĒā§ āϧāĻžāĻĒā§ āĻļā§āώ⧠āĻāĻāĻāĻĒā§āĻ = \(A \oplus B\) |
- āĻā§ā§āĻžāύā§āϤ āĻāĻāĻāĻĒā§āĻ = XOR Gate |
Universal Logic Gates using only NOR GatesÂļ
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đ Final Note:
đ āĻļā§āϧ⧠NAND Gate āĻ
āĻĨāĻŦāĻž āĻļā§āϧ⧠NOR Gate āĻĻāĻŋā§ā§āĻ āĻ
āύā§āϝ āϏāĻŦ Logic Gate āϤā§āϰāĻŋ āĻāϰāĻž āϝāĻžā§ | āĻāĻāύā§āϝ āĻāĻā§āϞā§āĻā§ āĻŦāϞāĻž āĻšā§ Universal Logic Gate |




