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DLD - Class 04Âļ

NAND Gate

NAND Gate Pin DiagramÂļ

NAND Gate Pin Diagram

NAND Gate Simplified DiagramÂļ

NAND Gate Simplified Diagram

NAND āϕ⧇ connection āĻĻā§‡ā§ŸāĻžāϰ āĻĒāϰ⧇ āĻāĻŽāύ āĻĻ⧇āĻ–āĻžāĻŦ⧇āσÂļ

DLD Lab NAND Gate Connection

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XOR Gate

XOR Gate Pin DiagramÂļ

XOR Gate Pin Diagram

XOR āϕ⧇ connection āĻĻā§‡ā§ŸāĻžāϰ āĻĒāϰ⧇ āĻāĻŽāύ āĻĻ⧇āĻ–āĻžāĻŦ⧇āσÂļ

XOR Gate Connection

XOR āϕ⧇ connection āĻĻā§‡ā§ŸāĻžāϰ āĻĒāϰ⧇ āĻāĻŽāύ āĻĻ⧇āĻ–āĻžāĻŦ⧇āσÂļ

DLD XOR Gate Connection Testing

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NOR Gate

NOR Gate Pin DiagramÂļ

NOR Gate Pin Diagram

NOR āϕ⧇ connection āĻĻā§‡ā§ŸāĻžāϰ āĻĒāϰ⧇ āĻāĻŽāύ āĻĻ⧇āĻ–āĻžāĻŦ⧇āσÂļ

NOR Gate Connection

NOR āϕ⧇ testing āĻ•āϰāϞ⧇ āĻļ⧁āϧ⧁ āĻŽāĻžāĻ¤ā§āϰ 00 āϤ⧇ LED āĻœā§āĻŦāϞāĻŦ⧇āσÂļ

NOR gate Corrected connection testing

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XNOR Gate

XNOR Gate with Truth tableÂļ

XNOR Gate with Truth table

XNOR āĻāϰ Simplified representation:Âļ

XNOR āĻāϰ Simplified representation
XNOR Simplified

XNOR Gate Connection:Âļ

XNOR Gate Connection

XNOR āϕ⧇ connection āĻĻā§‡ā§ŸāĻžāϰ āĻĒāϰ⧇ āĻāĻŽāύ āĻĻ⧇āĻ–āĻžāĻŦ⧇āσÂļ

XNOR gate Connection testing