Skip to content

DLD - Class 04

NAND Gate

NAND Gate Pin Diagram

NAND Gate Pin Diagram

NAND Gate Simplified Diagram

NAND Gate Simplified Diagram

NAND āϕ⧇ connection āĻĻā§‡ā§ŸāĻžāϰ āĻĒāϰ⧇ āĻāĻŽāύ āĻĻ⧇āĻ–āĻžāĻŦ⧇āσ

DLD Lab NAND Gate Connection

alt text

Try yourself:


XOR Gate

XOR Gate Pin Diagram

XOR Gate Pin Diagram

XOR āϕ⧇ connection āĻĻā§‡ā§ŸāĻžāϰ āĻĒāϰ⧇ āĻāĻŽāύ āĻĻ⧇āĻ–āĻžāĻŦ⧇āσ

XOR Gate Connection

XOR āϕ⧇ connection āĻĻā§‡ā§ŸāĻžāϰ āĻĒāϰ⧇ āĻāĻŽāύ āĻĻ⧇āĻ–āĻžāĻŦ⧇āσ

DLD XOR Gate Connection Testing

Try yourself:


NOR Gate

NOR Gate Pin Diagram

NOR Gate Pin Diagram

NOR āϕ⧇ connection āĻĻā§‡ā§ŸāĻžāϰ āĻĒāϰ⧇ āĻāĻŽāύ āĻĻ⧇āĻ–āĻžāĻŦ⧇āσ

NOR Gate Connection

NOR āϕ⧇ testing āĻ•āϰāϞ⧇ āĻļ⧁āϧ⧁ āĻŽāĻžāĻ¤ā§āϰ 00 āϤ⧇ LED āĻœā§āĻŦāϞāĻŦ⧇āσ

NOR gate Corrected connection testing

Try it yourself:

XNOR Gate

XNOR Gate with Truth table

XNOR Gate with Truth table

XNOR āĻāϰ Simplified representation:

XNOR āĻāϰ Simplified representation
XNOR Simplified

XNOR Gate Connection:

XNOR Gate Connection

XNOR āϕ⧇ connection āĻĻā§‡ā§ŸāĻžāϰ āĻĒāϰ⧇ āĻāĻŽāύ āĻĻ⧇āĻ–āĻžāĻŦ⧇āσ

XNOR gate Connection testing