Array Processing
āĻā§āĻŽāĻŋāĻāĻž: āĻāϰ⧠āĻĒā§āϰāϏā§āϏāϰ (Array Processor) āĻā§ āĻāĻŦāĻ āĻā§āύ āĻĒā§āϰā§ā§āĻāύ?¶
āĻāĻŽāĻžāĻĻā§āϰ āĻĻā§āύāύā§āĻĻāĻŋāύ āĻāĻŽā§āĻĒāĻŋāĻāĻāĻŋāĻā§ā§ āĻ āύā§āĻ āϏāĻŽā§ āĻāĻŽāύ āĻāĻŋāĻā§ āĻāĻžāĻŖāĻŋāϤāĻŋāĻ āĻ āĻŦā§āĻā§āĻāĻžāύāĻŋāĻ āϏāĻŽāϏā§āϝāĻž āĻāϏā§, āϝā§āĻāĻžāύ⧠āĻ āϤā§āϝāύā§āϤ āĻāĻāĻŋāϞ āĻāĻŦāĻ āĻŦāĻŋāĻļāĻžāϞ āĻĒāϰāĻŋāĻŽāĻžāĻŖā§āϰ āĻĄāĻžāĻāĻž (Massive and Complex Data) āĻĒā§āϰāϏā§āϏ āĻāϰāĻžāϰ āĻĒā§āϰā§ā§āĻāύ āĻšā§āĨ¤ āĻāĻĻāĻžāĻšāϰāĻŖāϏā§āĻŦāϰā§āĻĒ: āĻāĻŦāĻšāĻžāĻā§āĻž āĻĒā§āϰā§āĻŦāĻžāĻāĻžāϏ, āĻŦā§āĻā§āĻāĻžāύāĻŋāĻ āϏāĻŋāĻŽā§āϞā§āĻļāύ, āĻŦāĻž āĻā§āϰāĻžāĻĢāĻŋāĻā§āϏ āĻĒā§āϰāϏā§āϏāĻŋāĻāĨ¤
āĻāĻ āϧāϰāĻŖā§āϰ āĻŦāĻŋāĻļāĻžāϞ āĻĄāĻžāĻāĻž āĻāĻŽāϰāĻž āĻāĻāĻāĻŋ āϏāĻžāϧāĻžāϰāĻŖ āĻŦāĻž āϏāύāĻžāϤāύ āĻāĻŽā§āĻĒāĻŋāĻāĻāĻžāϰ (Conventional Computer) āĻĻāĻŋā§ā§āĻ āĻĒā§āϰāϏā§āϏ āĻāϰāĻžāϤ⧠āĻĒāĻžāϰāĻŋāĨ¤ āĻāĻŋāύā§āϤ⧠āϏāĻŽāϏā§āϝāĻž āĻšāϞā§, āϏāĻžāϧāĻžāϰāĻŖ āĻāĻŽā§āĻĒāĻŋāĻāĻāĻžāϰ āĻāĻ āĻĄāĻžāĻāĻžāĻā§āϞā§āĻā§ āĻāĻāĻāĻŋāϰ āĻĒāϰ āĻāĻāĻāĻŋ (Sequential) āĻĒā§āϰāϏā§āϏ āĻāϰā§āĨ¤ āĻĢāϞ⧠āĻāĻ āĻāĻāĻŋāϞ āĻĄāĻžāĻāĻž āĻāĻā§āϏāĻŋāĻāĻŋāĻāĻ āĻāϰāϤ⧠āĻāĻŽāĻžāĻĻā§āϰ āĻ āύā§āĻ āĻĻāĻŋāύ āĻŦāĻž āĻāĻŽāύāĻāĻŋ āĻā§ā§āĻ āϏāĻĒā§āϤāĻžāĻš āϏāĻŽā§ āϞā§āĻā§ āϝā§āϤ⧠āĻĒāĻžāϰā§āĨ¤
āĻāĻ āϏāĻŽāϏā§āϝāĻžāϰ āϏāĻŽāĻžāϧāĻžāύ āĻāĻŦāĻ āĻāĻŽā§āĻĒāĻŋāĻāĻāĻžāϰā§āϰ āĻāĻžāϰā§āϝāĻā§āώāĻŽāϤāĻž (Performance) āĻŦāĻšā§āĻā§āĻŖ āĻŦāĻžā§āĻŋā§ā§ āĻĻā§āϰā§āϤ āĻĢāϞāĻžāĻĢāϞ āĻĒāĻžāĻā§āĻžāϰ āĻāύā§āϝ āϏāĻŦāĻĨā§āĻā§ āϏā§āϰāĻž āĻŦāĻŋāĻāϞā§āĻĒ āĻšāϞ⧠āĻāϰ⧠āĻĒā§āϰāϏā§āϏāϰ (Array Processor)āĨ¤
- āĻŽā§āϞ āĻāĻžāĻ: āĻāϰ⧠āĻĒā§āϰāϏā§āϏāϰ āĻŽā§āϞāϤ āĻāĻāĻāĻŋ āĻŦāĻŋāĻļāĻžāϞ āĻĄāĻžāĻāĻžāϰ āĻ ā§āϝāĻžāϰ⧠(Large Array of Data)-āϰ āĻāĻĒāϰ āĻāĻŽā§āĻĒāĻŋāĻāĻā§āĻļāύ āĻŦāĻž āĻāĻŖāύāĻž āĻāϰā§āĨ¤
- āĻāĻžāĻā§āϰ āĻĒā§āϰāĻā§āϰāĻŋā§āĻž: āĻāĻŽāϰāĻž āϝāĻāύ āĻāĻ āĻŦāĻŋāĻļāĻžāϞ āĻĒāϰāĻŋāĻŽāĻžāĻŖā§āϰ āĻĄāĻžāĻāĻž āĻāϰ⧠āĻĒā§āϰāϏā§āϏāϰā§āϰ āĻāύāĻĒā§āĻ āĻšāĻŋāϏā§āĻŦā§ āĻĻāĻŋāĻ, āϤāĻāύ āĻāĻāĻŋ āĻ āϤā§āϝāύā§āϤ āĻĻā§āϰā§āϤ āĻ āύāĻŋāĻā§āĻāϤāĻāĻžāĻŦā§ (Fastly & Quickly) āĻĄāĻžāĻāĻžāĻā§āϞā§āĻā§ āĻāĻā§āϏāĻŋāĻāĻŋāĻāĻ āĻāϰ⧠āĻāĻŽāĻžāĻĻā§āϰ āĻāύā§āϝ āĻāĻāĻāĻĒā§āĻ āĻŦāĻž āϰā§āĻāĻžāϞā§āĻ āϤā§āϰāĻŋ āĻāϰ⧠āĻĻā§ā§āĨ¤
āĻāϰ⧠āĻĒā§āϰāϏā§āϏāϰā§āϰ āĻĒā§āϰāĻāĻžāϰāĻā§āĻĻ (Types of Array Processors)¶
āĻ āĻā§āϝāύā§āϤāϰā§āĻŖ āĻāĻ āύ āĻāĻŦāĻ āϏāĻāϝā§āĻā§āϰ āĻāĻĒāϰ āĻāĻŋāϤā§āϤāĻŋ āĻāϰ⧠āĻāϰ⧠āĻĒā§āϰāϏā§āϏāϰāĻā§ āĻŽā§āϞāϤ āĻĻā§āĻ āĻāĻžāĻā§ āĻāĻžāĻ āĻāϰāĻž āϝāĻžā§ āĻŦāĻž āĻĻā§āĻāĻŋ āĻāĻĒāĻžā§ā§ āϤā§āϰāĻŋ āĻāϰāĻž āϝāĻžā§:
- āĻ ā§āϝāĻžāĻāĻžāĻāĻĄ āĻāϰ⧠āĻĒā§āϰāϏā§āϏāϰ (Attached Array Processor)
- āĻāϏāĻāĻāĻāĻŽāĻĄāĻŋ āĻāϰ⧠āĻĒā§āϰāϏā§āϏāϰ (SIMD Array Processor)
āĻā§āϰā§āϤā§āĻŦāĻĒā§āϰā§āĻŖ āύā§āĻ: āĻāĻ āĻĻā§āĻāĻŋ āĻĒā§āϰāϏā§āϏāϰā§āϰāĻ āĻŽā§āϞ āϞāĻā§āώā§āϝ āĻāĻâāĻāĻā§āĻ āĻā§āĻā§āĻāϰ āĻāύāϏā§āĻā§āϰāĻžāĻāĻļāύ (Vector Instructions) āĻāĻā§āϏāĻŋāĻāĻŋāĻāĻ āĻāĻŦāĻ āĻŽā§āϝāĻžāύāĻŋāĻĒā§āϞā§āĻ āĻāϰā§āĨ¤ āĻĄāĻžāĻāĻž āĻĻā§āϰā§āϤ āĻĒā§āϰāϏā§āϏ āĻāϰāĻž āĻāĻŦāĻ āϏāĻŋāϏā§āĻā§āĻŽā§āϰ āĻāĻžāϰā§āϝāĻā§āώāĻŽāϤāĻž āĻŦāĻžā§āĻžāύā§āĻ āĻāĻĻā§āϰ āĻāĻžāĻāĨ¤ āĻāĻĻā§āϰ āĻŽāϧā§āϝ⧠āĻŽā§āϞ āĻĒāĻžāϰā§āĻĨāĻā§āϝāĻāĻŋ āĻšāϞ⧠āĻāĻĻā§āϰ āĻ āĻā§āϝāύā§āϤāϰā§āĻŖ āϏāĻžāĻāĻāĻ āύāĻŋāĻ āĻāĻžāĻ āĻžāĻŽā§ (Internal Organization) āĻŦāĻž āĻāϰā§āĻāĻŋāĻā§āĻāĻāĻžāϰā§āĨ¤
ā§§. āĻ ā§āϝāĻžāĻāĻžāĻāĻĄ āĻāϰ⧠āĻĒā§āϰāϏā§āϏāϰ (Attached Array Processor)¶
āĻ ā§āϝāĻžāĻāĻžāĻāĻĄ āĻāϰ⧠āĻĒā§āϰāϏā§āϏāϰ āĻšāϞ⧠āĻāĻŽāύ āĻāĻāĻāĻŋ āĻĒā§āϰāϏā§āϏāϰ āϝāĻž āϏā§āĻŦāĻžāϧā§āύāĻāĻžāĻŦā§ āĻāĻžāĻ āύāĻž āĻāϰ⧠āĻāĻāĻāĻŋ āϏāĻšāĻžā§āĻ āĻĒā§āϰāϏā§āϏāϰ (Auxiliary Processor) āĻšāĻŋāϏā§āĻŦā§ āĻāĻžāĻ āĻāϰā§āĨ¤ āĻāĻāĻŋāĻā§ āĻāĻāĻāĻŋ āϏāĻžāϧāĻžāϰāĻŖ āĻŦāĻž āϏāύāĻžāϤāύ āĻāĻŽā§āĻĒāĻŋāĻāĻāĻžāϰā§āϰ (General Purpose Computer) āϏāĻžāĻĨā§ āĻŦāĻžāĻšā§āϝāĻŋāĻ āĻĄāĻŋāĻāĻžāĻāϏ āĻŦāĻž āĻĒā§āϰāĻŋāĻĢā§āϰāĻžāϞ āĻĄāĻŋāĻāĻžāĻāϏ (Peripheral Device) āĻšāĻŋāϏā§āĻŦā§ āϝā§āĻā§āϤ āĻŦāĻž āĻ ā§āϝāĻžāĻāĻžāĻāĻĄ āĻāϰāĻž āĻšā§āĨ¤
āϝāĻāύāĻ āĻŽā§āĻāύ āĻāĻŽā§āĻĒāĻŋāĻāĻāĻžāϰā§āϰ āĻāĻžāĻā§ āĻā§āύ⧠āĻŦāĻŋāĻļāĻžāϞ āĻ āĻāĻāĻŋāϞ āĻĄāĻžāĻāĻžāϰ āĻ ā§āϝāĻžāϰ⧠āĻāϏā§, āϤāĻāύ āϏ⧠āύāĻŋāĻā§ āϤāĻž āĻĒā§āϰāϏā§āϏ āύāĻž āĻāϰ⧠āĻāĻ āĻ ā§āϝāĻžāĻāĻžāĻāĻĄ āĻāϰ⧠āĻĒā§āϰāϏā§āϏāϰā§āϰ āĻāĻžāĻā§ āĻĒāĻžāĻ āĻŋā§ā§ āĻĻā§ā§āĨ¤
āĻ āĻā§āϝāύā§āϤāϰā§āĻŖ āĻāĻ āύ āĻ āĻŦā§āϞāĻ āĻĄāĻžāϝāĻŧāĻžāĻā§āϰāĻžāĻŽā§āϰ āĻŦā§āϝāĻžāĻā§āϝāĻž:¶
āĻāĻāĻāĻŋ āĻ ā§āϝāĻžāĻāĻžāĻāĻĄ āĻāϰ⧠āĻĒā§āϰāϏā§āϏāϰ āϏāĻŋāϏā§āĻā§āĻŽ āĻŽā§āϞāϤ āύāĻŋāĻā§āϰ āĻ āĻāĻļāĻā§āϞ⧠āύāĻŋā§ā§ āĻāĻ āĻŋāϤ āĻšā§:
- āĻšā§āϏā§āĻ āĻāĻŽā§āĻĒāĻŋāĻāĻāĻžāϰ (Host / General Purpose Computer): āĻāĻāĻŋ āĻŽā§āϞ āĻāĻŽā§āĻĒāĻŋāĻāĻāĻžāϰ āϝāĻž āϏāĻžāϧāĻžāϰāĻŖ āĻāĻžāĻāĻā§āϞ⧠āύāĻŋā§āύā§āϤā§āϰāĻŖ āĻāϰā§āĨ¤
- āĻāύāĻĒā§āĻ-āĻāĻāĻāĻĒā§āĻ āĻāύā§āĻāĻžāϰāĻĢā§āϏ (I/O Interface): āĻšā§āϏā§āĻ āĻāĻŽā§āĻĒāĻŋāĻāĻāĻžāϰ āĻāĻŦāĻ āĻ ā§āϝāĻžāĻāĻžāĻāĻĄ āĻĒā§āϰāϏā§āϏāϰā§āϰ āĻāĻžāĻā§āϰ āĻāϤāĻŋ āĻāĻŦāĻ āĻ āĻā§āϝāύā§āϤāϰā§āĻŖ āĻāĻžāĻ āĻžāĻŽā§āϰ āĻŽāϧā§āϝ⧠āϝ⧠āĻĒāĻžāϰā§āĻĨāĻā§āϝ āĻŦāĻž āĻ āĻŽāĻŋāϞ āĻĨāĻžāĻā§, āϤāĻž āĻĻā§āϰ āĻŦāĻž āϰāĻŋāĻāϞāĻ (Resolve) āĻāϰāĻžāϰ āĻāĻžāĻ āĻāϰ⧠āĻāĻ āĻāύā§āĻāĻžāϰāĻĢā§āϏāĻāĻŋāĨ¤
- āĻŽā§āĻāύ āĻŽā§āĻŽā§āϰāĻŋ (Main Memory): āĻāĻāĻŋ āĻšā§āϏā§āĻ āĻāĻŽā§āĻĒāĻŋāĻāĻāĻžāϰā§āϰ āύāĻŋāĻāϏā§āĻŦ āĻŽā§āĻŽā§āϰāĻŋ, āϝā§āĻāĻžāύ⧠āϏāĻŽāϏā§āϤ āĻĒā§āϰāĻžāĻĨāĻŽāĻŋāĻ āĻāύāϏā§āĻā§āϰāĻžāĻāĻļāύ āĻāĻŦāĻ āĻĄāĻžāĻāĻž āĻāĻŽāĻž āĻĨāĻžāĻā§āĨ¤
- āϞā§āĻāĻžāϞ āĻŽā§āĻŽā§āϰāĻŋ (Local Memory): āĻāĻāĻŋ āϏā§āĻŦā§āĻ āĻāϰ⧠āĻĒā§āϰāϏā§āϏāϰā§āϰ āύāĻŋāĻāϏā§āĻŦ āĻŽā§āĻŽā§āϰāĻŋāĨ¤
- āĻšāĻžāĻ-āϏā§āĻĒāĻŋāĻĄ āĻŽā§āĻŽā§āϰāĻŋ-āĻā§-āĻŽā§āĻŽā§āϰāĻŋ āĻŦāĻžāϏ (High-Speed Memory-to-Memory Bus): āĻŽā§āĻāύ āĻŽā§āĻŽā§āϰāĻŋ āĻāĻŦāĻ āϞā§āĻāĻžāϞ āĻŽā§āĻŽā§āϰāĻŋāĻā§ āϏāϰāĻžāϏāϰāĻŋ āϝā§āĻā§āϤ āĻāϰāĻžāϰ āĻāύā§āϝ āĻāĻ āĻŦāĻŋāĻļā§āώ āĻ āĻĻā§āϰā§āϤāĻāϤāĻŋāϰ āĻŦāĻžāϏāĻāĻŋ āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻāϰāĻž āĻšā§āĨ¤
āĻāĻžāϰā§āϝāĻĒāĻĻā§āϧāϤāĻŋ āĻ āĻĄāĻžāĻāĻž āĻĢā§āϞ⧠(Working & Data Flow):¶
- āĻāĻŽā§āĻĒāĻŋāĻāĻāĻžāϰā§āϰ āϏāĻŽāϏā§āϤ āĻāύāϏā§āĻā§āϰāĻžāĻāĻļāύ āĻāĻŦāĻ āĻŽā§āϝāĻžāϏāĻŋāĻ āĻĄāĻžāĻāĻž āϏāĻŦāĻžāϰ āĻĒā§āϰāĻĨāĻŽā§ āĻšā§āϏā§āĻ āĻāĻŽā§āĻĒāĻŋāĻāĻāĻžāϰā§āϰ Main Memory-āϤ⧠āϏā§āĻā§āϰ āĻŦāĻž āĻāĻŽāĻž āĻšā§āĨ¤
- āĻāϰāĻĒāϰ, Massive/Complex Data â High-Speed Memory-to-Memory Bus āĻĻāĻŋāϝāĻŧā§ Local Memory-āϤ⧠transfer āĻšāϝāĻŧ
- āϞā§āĻāĻžāϞ āĻŽā§āĻŽā§āϰāĻŋāϤ⧠āĻĄāĻžāĻāĻž āĻāϏāĻžāϰ āĻĒāϰ, āĻāϰ⧠āĻĒā§āϰāϏā§āϏāϰ āϏā§āĻāĻžāύ āĻĨā§āĻā§ āĻĄāĻžāĻāĻž āĻĢā§āϝāĻžāĻ (Fetch) āĻāϰā§āĨ¤
- āĻāĻāĻžāύ⧠āĻĒā§āϰāϏā§āϏāĻŋāĻā§ā§āϰ āĻāĻžāĻ āĻāĻāĻž āĻšā§ āύāĻž; āĻŦāϰāĻ āĻāĻāĻŋāϞ āĻā§āϝāĻžāϞāĻā§āϞā§āĻļāύāĻā§āϞā§āĻā§ āĻŽāĻžāϞā§āĻāĻŋāĻĒāϞ āĻĢāĻžāĻāĻļāύāĻžāϞ āĻāĻāύāĻŋāĻā§āϰ (Multiple Functional Units) āĻŽāĻžāϧā§āϝāĻŽā§ āϏāĻŽāĻžāύā§āϤāϰāĻžāϞāĻāĻžāĻŦā§ āĻŦāĻž āĻĒā§āϝāĻžāϰāĻžāϞāĻžāϞāĻŋ (Parallelly) āĻāĻā§āϏāĻŋāĻāĻŋāĻāĻ āĻāϰāĻž āĻšā§āĨ¤ āĻāϰ āĻĢāϞ⧠āĻĒā§āϰāϏā§āϏāĻŋāĻ āϏā§āĻĒāĻŋāĻĄ āĻ āύā§āĻ āĻšāĻžāĻ (High Performance) āĻšā§āĨ¤
- āĻāĻā§āϏāĻŋāĻāĻŋāĻāĻļāύ āĻļā§āώ āĻšāĻā§āĻžāϰ āĻĒāϰ āĻāϰ⧠āĻĒā§āϰāϏā§āϏāϰ āĻĢāϞāĻžāĻĢāϞāĻāĻŋāĻā§ āĻĒā§āύāϰāĻžā§ āϤāĻžāϰ Local Memory-āϤ⧠āϏā§āĻ āĻāϰā§āĨ¤
- āϏāĻŦāĻļā§āώā§, āϞā§āĻāĻžāϞ āĻŽā§āĻŽā§āϰāĻŋ āĻĨā§āĻā§ āϏā§āĻ āĻāĻāĻāĻĒā§āĻ āĻŦāĻž āϰā§āĻāĻžāϞā§āĻ āĻāĻŦāĻžāϰ āĻšāĻžāĻ-āϏā§āĻĒāĻŋāĻĄ āĻŦāĻžāϏā§āϰ āĻŽāĻžāϧā§āϝāĻŽā§ āĻŽā§āĻāύ āĻāĻŽā§āĻĒāĻŋāĻāĻāĻžāϰā§āϰ Main Memory-āϤ⧠āĻĢā§āϰāϤ āĻāϞ⧠āĻāϏā§āĨ¤ āĻāĻāĻžāĻŦā§āĻ āĻĒā§āϰ⧠āĻāĻžāϰā§āϝāĻĒā§āϰāĻā§āϰāĻŋā§āĻž āϏāĻŽā§āĻĒāύā§āύ āĻšā§āĨ¤
⧍. āĻāϏāĻāĻāĻāĻŽāĻĄāĻŋ āĻāϰ⧠āĻĒā§āϰāϏā§āϏāϰ (SIMD Array Processor)¶
SIMD-āĻāϰ āĻĒā§āϰā§āĻŖāϰā§āĻĒ āĻšāϞ⧠Single Instruction Stream, Multiple Data Stream (āĻāĻāĻ āĻāύāϏā§āĻā§āϰāĻžāĻāĻļāύ āϏā§āĻā§āϰāĻŋāĻŽ āĻāĻŦāĻ āĻāĻāĻžāϧāĻŋāĻ āĻĄāĻžāĻāĻž āϏā§āĻā§āϰāĻŋāĻŽ)āĨ¤ āĻāϰ āύāĻžāĻŽ āĻĨā§āĻā§āĻ āĻŦā§āĻāĻž āϝāĻžā§ āϝā§, āĻāĻāĻžāύ⧠āĻāύāϏā§āĻā§āϰāĻžāĻāĻļāύ āĻŦāĻž āĻāĻŽāĻžāύā§āĻĄ āĻĨāĻžāĻāĻŦā§ āĻŽāĻžāϤā§āϰ āĻāĻāĻāĻŋ, āĻāĻŋāύā§āϤ⧠āϏā§āĻ āĻāĻāĻāĻŋ āĻāĻŽāĻžāύā§āĻĄ āĻāĻāĻ āϏāĻŽā§ā§ āĻāϞāĻžāĻĻāĻž āĻāϞāĻžāĻĻāĻž āĻ āύā§āĻāĻā§āϞ⧠āĻĄāĻžāĻāĻžāϰ āĻāĻĒāϰ āĻāĻžāĻ āĻāϰāĻŦā§āĨ¤
āĻāĻ āϏāĻŋāϏā§āĻā§āĻŽā§ āĻāĻāĻāĻŋ āĻŦāĻŋāĻļāĻžāϞ āĻĄāĻžāĻāĻžāϰ āĻ ā§āϝāĻžāϰā§āĻā§ āĻĒā§āϝāĻžāϰāĻžāϞāĻžāϞāĻŋ āĻāĻā§āϏāĻŋāĻāĻŋāĻāĻ āĻāϰāĻžāϰ āĻāύā§āϝ āĻŽā§āϝāĻžāϞā§āĻāĻŋāĻĒāϞ āĻĒā§āϰāϏā§āϏāĻŋāĻ āĻāĻāύāĻŋāĻ (Multiple Processing Units) āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻāϰāĻž āĻšā§āĨ¤
āĻ āĻā§āϝāύā§āϤāϰā§āĻŖ āĻāĻ āύ āĻ āĻŦā§āϞāĻ āĻĄāĻžāϝāĻŧāĻžāĻā§āϰāĻžāĻŽā§āϰ āĻŦā§āϝāĻžāĻā§āϝāĻž:¶
āĻāϏāĻāĻāĻāĻŽāĻĄāĻŋ āĻāϰ⧠āĻĒā§āϰāϏā§āϏāϰā§āϰ āĻāϰā§āĻāĻŋāĻā§āĻāĻāĻžāϰ āĻŦāĻž āĻāĻ āύ āύāĻŋāĻā§ āĻĻā§āĻā§āĻž āĻšāϞā§:

* āĻāĻŽāύ āĻāύā§āĻā§āϰā§āϞ āĻāĻāύāĻŋāĻ (Common Control Unit / Master CPU): āĻāĻāĻŋ āĻĒā§āϰ⧠āϏāĻŋāϏā§āĻā§āĻŽā§āϰ āĻŽāĻžāĻĨāĻž āĻŦāĻž āĻŽāĻžāϏā§āĻāĻžāϰ āĻĒā§āϰāϏā§āϏāϰāĨ¤ āĻāϰ āĻāĻžāĻ āĻšāϞ⧠āĻāύāϏā§āĻā§āϰāĻžāĻāĻļāύ āĻŽā§āĻāύ āĻŽā§āĻŽā§āϰāĻŋ āĻĨā§āĻā§ āĻāύāĻž āĻāĻŦāĻ āύāĻŋāĻā§āϰ āĻĒā§āϰāϏā§āϏāĻŋāĻ āĻāϞāĻŋāĻŽā§āύā§āĻāĻā§āϞā§āĻā§ āύāĻŋā§āύā§āϤā§āϰāĻŖ āĻāϰāĻžāĨ¤
* āĻŽā§āĻāύ āĻŽā§āĻŽā§āϰāĻŋ (Main Memory): āĻŽāĻžāϏā§āĻāĻžāϰ āϏāĻŋāĻĒāĻŋāĻāĻ-āĻāϰ āϏāĻžāĻĨā§ āĻŽā§āĻāύ āĻŽā§āĻŽā§āϰāĻŋ āϝā§āĻā§āϤ āĻĨāĻžāĻā§, āϝā§āĻāĻžāύ⧠āĻĒā§āϰāϏā§āϏ āĻāϰāĻžāϰ āĻŽāϤ⧠āϏāĻŽāϏā§āϤ āĻāύāϏā§āĻā§āϰāĻžāĻāĻļāύ āĻāĻŽāĻž āĻĨāĻžāĻā§āĨ¤
* āĻĒā§āϰāϏā§āϏāĻŋāĻ āĻāϞāĻŋāĻŽā§āύā§āĻāϏ (Processing Elements - PE): āĻāĻāĻžāύ⧠āĻ
āύā§āĻāĻā§āϞ⧠āĻĒā§āϰāϏā§āϏāϰ āĻĒā§āϝāĻžāϰāĻžāϞāĻžāϞāĻŋ āĻŦāϏāĻžāύ⧠āĻĨāĻžāĻā§, āϝāĻžāĻĻā§āϰ \(PE_1, PE_2, PE_3 ... PE_n\) āĻŦāϞāĻž āĻšā§āĨ¤
* āϞā§āĻāĻžāϞ āĻŽā§āĻŽā§āϰāĻŋ (Local Memory - M): āĻĒā§āϰāϤāĻŋāĻāĻŋ āĻĒā§āϰāϏā§āϏāĻŋāĻ āĻāϞāĻŋāĻŽā§āύā§āĻā§āϰ (PE) āύāĻŋāĻāϏā§āĻŦ āĻāϞāĻžāĻĻāĻž āϞā§āĻāĻžāϞ āĻŽā§āĻŽā§āϰāĻŋ āĻĨāĻžāĻā§, āϝā§āĻā§āϞā§āĻā§ \(M_1, M_2, M_3 ... M_n\) āĻŦāϞāĻž āĻšā§āĨ¤ āĻāĻāĻžā§āĻžāĻ āĻĒā§āϰāϤāĻŋāĻāĻŋ PE-āϰ āύāĻŋāĻāϏā§āĻŦ āϰā§āĻāĻŋāϏā§āĻāĻžāϰ āĻāĻŦāĻ I/O āĻĄāĻŋāĻāĻžāĻāϏ āĻĨāĻžāĻā§āĨ¤
* āϏāĻŋāĻā§āĻā§āϰā§āύāĻžāĻāĻā§āĻļāύ āϏāĻāϝā§āĻ: āĻŽāĻžāϏā§āĻāĻžāϰ āϏāĻŋāĻĒāĻŋāĻāĻ āĻŦāĻž āĻāĻŽāύ āĻāύā§āĻā§āϰā§āϞ āĻāĻāύāĻŋāĻāĻāĻŋ āĻĒā§āϰāϤāĻŋāĻāĻŋ āĻĒā§āϰāϏā§āϏāĻŋāĻ āĻāϞāĻŋāĻŽā§āύā§āĻā§āϰ āϏāĻžāĻĨā§ āϏāϰāĻžāϏāϰāĻŋ āϝā§āĻā§āϤ āĻĨāĻžāĻā§ āϝāĻžāϤ⧠āϏāĻŦāĻžāĻāĻā§ āĻāĻāϏāĻžāĻĨā§ āĻāĻāĻ āϤāĻžāϞ⧠(Synchronized āĻāĻžāĻŦā§) āĻāĻžāϞāĻžāύ⧠āϝāĻžā§āĨ¤
āĻāĻŋāĻĄāĻŋāĻāϰ āĻāĻĻāĻžāĻšāϰāĻŖāϏāĻš āĻāĻžāϰā§āϝāĻĒāĻĻā§āϧāϤāĻŋ:¶
āϧāϰāĻž āϝāĻžāĻ, āĻāĻŽāĻžāĻĻā§āϰ āĻāĻāĻāĻŋ āĻāĻžāĻŖāĻŋāϤāĻŋāĻ āĻ āĻĒāĻžāϰā§āĻļāύ āĻāϰāϤ⧠āĻšāĻŦā§, āϝā§āĻāĻžāύ⧠āĻĻā§āĻāĻŋ āĻ ā§āϝāĻžāϰā§āĻā§ āϝā§āĻ āĻāϰāϤ⧠āĻšāĻŦā§:
āĻāĻāĻžāύ⧠\(A\) āĻāĻŦāĻ \(B\) āĻšāϞ⧠āĻĄāĻžāĻāĻžāϰ āĻĻā§āĻāĻŋ āĻŦāĻŋāĻļāĻžāϞ āĻ ā§āϝāĻžāϰā§, āϝāĻž āĻŽā§āĻāύ āĻŽā§āĻŽā§āϰāĻŋāϤ⧠āĻāĻā§āĨ¤ āĻŽāĻžāϏā§āĻāĻžāϰ āϏāĻŋāĻĒāĻŋāĻāĻ āĻŽā§āĻāύ āĻŽā§āĻŽā§āϰāĻŋ āĻĨā§āĻā§ āĻāĻāĻāĻŋ āĻŽāĻžāϤā§āϰ āĻāύāϏā§āĻā§āϰāĻžāĻāĻļāύ āĻŦāĻž āύāĻŋāϰā§āĻĻā§āĻļ āĻāύāĻŦā§, āϤāĻž āĻšāϞā§â"āϝā§āĻ (Addition) āĻāϰā§"āĨ¤ āĻāĻŋāύā§āϤ⧠āĻĄāĻžāĻāĻž āĻāϞāĻžāĻĻāĻž āĻāϞāĻžāĻĻāĻž āĻĒā§āϰāϏā§āϏāĻŋāĻ āĻāϞāĻŋāĻŽā§āύā§āĻā§ āĻāĻžāĻ āĻšā§ā§ āϝāĻžāĻŦā§:
- \(PE_1\) (āĻĒā§āϰāϏā§āϏāĻŋāĻ āĻāϞāĻŋāĻŽā§āύā§āĻ ā§§): āϤāĻžāϰ āύāĻŋāĻāϏā§āĻŦ āĻŽā§āĻŽā§āϰāĻŋ \(M_1\) āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻāϰ⧠āĻāĻāĻ āϏāĻŽā§ā§ āϝā§āĻ āĻāϰāĻŦā§ \(A_1 + B_1\)
- \(PE_2\) (āĻĒā§āϰāϏā§āϏāĻŋāĻ āĻāϞāĻŋāĻŽā§āύā§āĻ ā§¨): āϤāĻžāϰ āύāĻŋāĻāϏā§āĻŦ āĻŽā§āĻŽā§āϰāĻŋ \(M_2\) āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻāϰ⧠āĻāĻāĻ āϏāĻŽā§ā§ āϝā§āĻ āĻāϰāĻŦā§ \(A_2 + B_2\)
- \(PE_3\) (āĻĒā§āϰāϏā§āϏāĻŋāĻ āĻāϞāĻŋāĻŽā§āύā§āĻ ā§Š): āϝā§āĻ āĻāϰāĻŦā§ \(A_3 + B_3\)
- \(PE_n\) (āĻĒā§āϰāϏā§āϏāĻŋāĻ āĻāϞāĻŋāĻŽā§āύā§āĻ \(n\)): āĻļā§āώ āĻĄāĻžāĻāĻžāĻāĻŋ āϝā§āĻ āĻāϰāĻŦā§ \(A_n + B_n\)
āĻĢāϞāĻžāĻĢāϞ: āϝā§āĻšā§āϤ⧠āϏāĻŽāϏā§āϤ āĻĒā§āϰāϏā§āϏāĻŋāĻ āĻāϞāĻŋāĻŽā§āύā§āĻ (PE) āĻāĻāĻ āϏāĻŽā§ā§ āĻĒā§āϝāĻžāϰāĻžāϞāĻžāϞāĻŋ āύāĻŋāĻ āύāĻŋāĻ āĻĄāĻžāĻāĻžāϰ āĻāĻĒāϰ āĻāĻžāĻ āĻāϰāĻā§, āϤāĻžāĻ āϏāĻŋāϏā§āĻā§āĻŽā§āϰ āĻĨā§āϰā§āĻāĻĒā§āĻ (Throughput) āĻŦāĻž āĻāĻāĻāĻĒā§āĻ āĻĻā§āĻā§āĻžāϰ āĻāϤāĻŋ āĻā§ā§āĻ āĻā§āĻŖ āĻŦā§ā§ā§ āϝāĻžā§ āĻāĻŦāĻ āĻā§āĻŦ āĻĻā§āϰā§āϤ āĻĢāϞāĻžāĻĢāϞ āĻĒāĻžāĻā§āĻž āϝāĻžā§āĨ¤
āϏāĻžāϰāϏāĻāĻā§āώā§āĻĒ (Conclusion)¶
āĻāĻŋāĻĄāĻŋāĻāϰ āĻĒāϰāĻŋāĻļā§āώ⧠āĻāĻŽāϰāĻž āĻāĻžāύāϤ⧠āĻĒāĻžāϰāϞāĻžāĻŽ āϝā§, āĻāϰ⧠āĻĒā§āϰāϏā§āϏāϰ āĻšāϞ⧠āϞāĻžāϰā§āĻ āĻĄāĻžāĻāĻž āϏā§āĻāĻā§ āĻĻā§āϰā§āϤ āĻĒā§āϰāϏā§āϏ āĻāϰāĻžāϰ āĻāĻāĻāĻŋ āĻ āϤā§āϝāύā§āϤ āĻļāĻā§āϤāĻŋāĻļāĻžāϞ⧠āĻŽāĻžāϧā§āϝāĻŽāĨ¤
- āĻ ā§āϝāĻžāĻāĻžāĻāĻĄ āĻāϰ⧠āĻĒā§āϰāϏā§āϏāϰ⧠āĻāĻŽāϰāĻž āϏāĻžāϧāĻžāϰāĻŖ āĻāĻŽā§āĻĒāĻŋāĻāĻāĻžāϰā§āϰ āϏāĻžāĻĨā§ āĻāĻāĻāĻŋ āĻāĻā§āϏāĻāĻžāϰā§āύāĻžāϞ āĻ āĻā§āϏāĻŋāϞāĻžāϰāĻŋ āĻĒā§āϰāϏā§āϏāϰ āϝā§āĻā§āϤ āĻāϰ⧠āĻŽā§āĻŽā§āϰāĻŋ-āĻā§-āĻŽā§āĻŽā§āϰāĻŋ āĻŦāĻžāϏā§āϰ āĻŽāĻžāϧā§āϝāĻŽā§ āĻĒā§āϝāĻžāϰāĻžāϞāĻžāϞ āĻĒā§āϰāϏā§āϏāĻŋāĻ āĻāϰāĻŋāĨ¤
- āĻ āύā§āϝāĻĻāĻŋāĻā§, āĻāϏāĻāĻāĻāĻŽāĻĄāĻŋ āĻāϰ⧠āĻĒā§āϰāϏā§āϏāϰ⧠āĻāĻāĻāĻŋ āϏā§āύā§āĻā§āϰāĻžāϞ āĻŽāĻžāϏā§āĻāĻžāϰ āϏāĻŋāĻĒāĻŋāĻāĻ-āĻāϰ āĻ āϧā§āύ⧠āĻ āύā§āĻāĻā§āϞ⧠āĻĒā§āϰāϏā§āϏāĻŋāĻ āĻāϞāĻŋāĻŽā§āύā§āĻ (PE) āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻāϰ⧠āĻāĻāĻ āύāĻŋāϰā§āĻĻā§āĻļ āĻĻāĻŋā§ā§ āĻāĻŋāύā§āύ āĻāĻŋāύā§āύ āĻĄāĻžāĻāĻžāϰ āĻāĻĒāϰ āĻāĻāϏāĻžāĻĨā§ āĻāĻžāĻ āĻāϰāĻŋā§ā§ āĻĻā§āϰā§āϤāϤāĻŽ āϏāĻŽā§ā§ āύāĻŋāĻā§āĻāϤ āĻāĻāĻāĻĒā§āĻ āϞāĻžāĻ āĻāϰāĻŋāĨ¤
Introduction: What is an Array Processor & Why Do We Need It?¶
In modern computing, we often encounter complex scientific or mathematical problems that involve processing a vast amount of data, known as Massive and Complex Data (e.g., weather forecasting, graphics rendering, aerodynamic simulations).
We can technically execute this massive and complex data using a conventional or traditional computer. However, because a conventional computer processes data sequentially (one after another), executing such complex datasets could take days or even several weeks.
To overcome this limitation, optimize system performance, and obtain rapid outputs, the best alternative is to use an Array Processor.
- Core Function: An array processor is specifically designed to perform computations on a large array of data.
- Working Process: When we feed a large array of data into an array processor, it executes the operations extremely fast and generates the final output almost instantly.
Types of Array Processors¶
Based on their internal architecture and how they are integrated into a system, array processors can be structured in two ways:
- Attached Array Processor
- SIMD Array Processor
Key Takeaway: Ultimately, both types of array processors serve the same objectiveâthey execute and manipulate Vector Instructions. Their primary goal is to accelerate computation and elevate system performance; they only differ in their Internal Organization and architectural design.
1. Attached Array Processor¶
An Attached Array Processor is not an independent system; rather, it acts as an Auxiliary Processor. It is connected as a peripheral or external device to a standard, traditional host computer (General Purpose Computer).
Whenever the host computer receives massive array-structured datasets, it offloads the heavy computation tasks to the attached array processor to enhance execution speed.
Internal Architecture & Block Diagram Explanation:¶
An Attached Array Processor system consists of the following fundamental blocks:
- Host Computer (General Purpose Computer): The main computer that manages standard system operations and controls the workflow.
- Input-Output (I/O) Interface: This interface connects the host computer with the attached processor. Its primary job is to resolve any architectural or speed differences between the two units.
- Main Memory: The host computer's proprietary memory where all primary instructions and incoming data are originally stored.
- Local Memory: The dedicated internal memory belonging strictly to the attached array processor.
- High-Speed Memory-to-Memory Bus: A dedicated, ultra-fast bus used to establish a direct connection between the Main Memory of the host and the Local Memory of the array processor.
Working Mechanism & Data Flow:¶
- All instructions and massive datasets are initially stored in the Main Memory of the host computer.
- The complex and large array of data is then transferred from the Main Memory to the Local Memory of the attached array processor via the High-Speed Memory-to-Memory Bus.
- Once the data lands in the local memory, the attached array processor fetches it for execution.
- Instead of executing the data sequentially, the complex tasks are distributed across Multiple Functional Units to be processed simultaneously or in parallel (Parallel Processing). This architecture ensures exceptionally high performance.
- After completing the execution, the array processor stores the computed results back into its Local Memory.
- Finally, these results/outputs are routed back from the Local Memory to the Main Memory of the host computer via the high-speed bus, completing the execution cycle.
2. SIMD Array Processor¶
SIMD stands for Single Instruction Stream, Multiple Data Stream. As the name implies, the system receives only a single instruction or command from the control unit, but that identical command is executed simultaneously across multiple distinct pieces of data.
This system uses Multiple Processing Units running synchronously to compute large arrays of data in parallel.
Internal Architecture & Block Diagram Explanation:¶
The architectural layout of an SIMD Array Processor includes:

* Common Control Unit (Master CPU): This is the brain or master controller of the entire architecture. It fetches instructions from the memory and orchestrates the processing elements.
* Main Memory: Directly connected to the Master CPU, this memory holds all the primary instructions waiting to be executed.
* Processing Elements (PE): This consists of an array of multiple parallel processing units designated as \(PE_1, PE_2, PE_3 ... PE_n\).
* Local Memory (M): Every individual Processing Element (PE) has its own dedicated local memory unit, labeled as \(M_1, M_2, M_3 ... M_n\), along with its own set of registers and I/O handlers.
* Synchronization Link: The Common Control Unit is directly connected to every single Processing Element, ensuring that all PEs perform operations in perfect synchronization.
Working Mechanism with the Video Example:¶
Let's understand the execution flow using the exact example from the video. Suppose we need to perform an array addition operation:
Here, \(A\) and \(B\) are large data arrays stored in the Main Memory. The Master CPU fetches a single instruction from the memory, which is "ADD". While the instruction remains a single command, the actual data arrays are divided among the multiple Processing Elements (PEs):
- \(PE_1\) (Processing Element 1): Utilizes its local memory \(M_1\) to simultaneously execute: \(A_1 + B_1\)
- \(PE_2\) (Processing Element 2): Utilizes its local memory \(M_2\) to simultaneously execute: \(A_2 + B_2\)
- \(PE_3\) (Processing Element 3): Simultanously executes: \(A_3 + B_3\)
- \(PE_n\) (Processing Element \(n\)): Executes the final data set in the array: \(A_n + B_n\)
Result: Because all the Processing Elements (PEs) are executing their designated data chunks at the exact same time (parallelly), the system's Throughput (output rate) increases exponentially, producing final results rapidly.
Summary (Conclusion)¶
To conclude based on the video lecture, an array processor is a highly powerful architectural component designed to fast-track large datasets.
- In an Attached Array Processor, we link an external auxiliary processor to a conventional host computer and achieve parallel processing via a high-speed memory-to-memory bus.
- In an SIMD Array Processor, we leverage multiple Processing Elements (PEs) controlled by a central Master CPU to run a single instruction over multiple data streams synchronously, maximizing computational speed and efficiency.