Skip to content

DLD - Lab BasicsÂļ


Breadboard

breadboard-full-hd

🌱 Part-1: Breadboard āϕ⧀?Âļ

Breadboard āĻšāϞ⧋ āĻāĻ•āϟāĻž plastic board āϝ⧇āϟāĻžāϰ āĻŽāĻ§ā§āϝ⧇ āĻ…āύ⧇āĻ•āϗ⧁āϞ⧋ āϛ⧋āϟ āϛ⧋āϟ hole (āĻ—āĻ°ā§āϤ) āĻĨāĻžāϕ⧇āĨ¤
āĻāχ hole-āϗ⧁āϞ⧋āϰ āĻ­āĻŋāϤāϰ⧇ metal clips/strips āϞ⧁āĻ•āĻžāύ⧋ āĻĨāĻžāϕ⧇ → āĻāϗ⧁āϞ⧋āχ āύāĻŋāĻ°ā§āĻĻāĻŋāĻˇā§āϟāĻ­āĻžāĻŦ⧇ āĻāϕ⧇ āĻ…āĻĒāϰ⧇āϰ āϏāĻžāĻĨ⧇ connectedāĨ¤

👉 āϤ⧁āĻŽāĻŋ āĻāĻ•āϟāĻž āϤāĻžāϰ (wire) āϝāĻĻāĻŋ āĻāĻ•āϟāĻž hole-āĻ āĻĸ⧁āĻ•āĻžāĻ“ āφāϰ āĻāĻ•āχ row-āĻāϰ āĻ…āĻ¨ā§āϝ hole-āĻ āĻĸā§‹āĻ•āĻžāĻ“, āϏ⧇āϟāĻž āĻāĻ•āχ āĻŦ⧈āĻĻā§āϝ⧁āϤāĻŋāĻ• āϞāĻžāχāύ (electrical connection) āĻšāĻŦ⧇āĨ¤

Analogy

Breadboard = āĻ¸ā§āϕ⧁āϞ⧇āϰ āĻŦ⧇āĻžā§āϚ
- āĻŦ⧇āĻžā§āĻšā§‡ āĻĒāĻžāρāϚāϜāύ āĻŦāĻžāĻšā§āϚāĻž āĻĒāĻžāĻļāĻžāĻĒāĻžāĻļāĻŋ āĻŦāϏāϞ⧇ āϤāĻžāϰāĻž āϏāĻŦāĻžāχ āĻāĻ• āĻŦ⧇āĻžā§āĻšā§‡ (connected)āĨ¤
- āĻ•āĻŋāĻ¨ā§āϤ⧁ āĻĒāĻžāĻļ⧇āϰ āĻŦ⧇āĻžā§āĻšā§‡ āĻŦāϏāĻž āĻŦāĻžāĻšā§āϚāĻžāĻĻ⧇āϰ āϏāĻžāĻĨ⧇ āϤāĻžāĻĻ⧇āϰ direct connection āύ⧇āχ ❌āĨ¤


🧩 Part-2: āĻ­āĻŋāϤāϰ⧇āϰ Connection SecretÂļ

⚡ Breadboard āφāϏāϞ⧇ āĻ­āĻŋāϤāϰ⧇ āϕ⧀āĻ­āĻžāĻŦ⧇ connected?Âļ

breadboard-details
Breadboard āĻāϰ holes āϗ⧁āϞ⧋ āϏāĻŦ āφāϞāĻžāĻĻāĻž āύāĻžāĨ¤ āϭ⧇āϤāϰ⧇ hidden metal strips āφāϛ⧇āĨ¤

  • āĻŽāĻžāĻāĻ–āĻžāύ⧇:

  • āĻāĻ• row-āĻāϰ A–E āĻāĻ•āϏāĻžāĻĨ⧇ connected ✅

  • āĻāĻ•āχ row-āĻāϰ F–J āĻāĻ•āϏāĻžāĻĨ⧇ connected ✅
  • āĻ•āĻŋāĻ¨ā§āϤ⧁ A–E āφāϰ F–J āĻāϕ⧇ āĻ…āĻĒāϰ⧇āϰ āϏāĻžāĻĨ⧇ connected āύāĻž ❌
  • āĻŽāĻžāĻāĻ–āĻžāύ⧇āϰ gap āϟāĻž āφāϏāϞ⧇ IC āĻŦāϏāĻžāύ⧋āϰ āϜāĻžā§ŸāĻ—āĻžāĨ¤

  • āĻĒāĻžāĻļ⧇: āϞāĻŽā§āĻŦāĻž āĻĻ⧁āχāϟāĻž line āĻĨāĻžāϕ⧇ (Power rail)

  • āϞāĻžāϞ ( + ) → Vcc (+5V)

  • āύ⧀āϞ/āĻ•āĻžāϞ⧋ ( – ) → GND (0V)

📊 Quick Table (Who connects to whom?)Âļ

Section Connection Rule
A–E row āĻāϕ⧇ āĻ…āĻĒāϰ⧇āϰ āϏāĻžāĻĨ⧇ shorted (internal metal strip) ✅
F–J row āĻāϕ⧇ āĻ…āĻĒāϰ⧇āϰ āϏāĻžāĻĨ⧇ shorted ✅
Gap Left vs Right side NOT connected ❌
Power Rail + āϏāĻŦ āϞāĻžāϞ hole āϏāĻžāϧāĻžāϰāĻŖāϤ connected (āĻ•āĻ–āύ⧋ āĻŽāĻžāĻāĻ–āĻžāύ⧇ break âš ī¸)
Power Rail – āϏāĻŦ āύ⧀āϞ hole āϏāĻžāϧāĻžāϰāĻŖāϤ connected

Part-4: Breadboard āĻāϰ Evolution / TimelineÂļ

  • 1940s: Wooden breadboard-āĻ actual nails āĻĻāĻŋāϝāĻŧ⧇ circuit āĻŦāĻžāύāĻžāύ⧋ āĻšāϤ⧋āĨ¤
  • 1970s: Plastic solderless breadboard āωāĻĻā§āĻ­āĻžāĻŦāĻŋāϤ āĻšāϝāĻŧāĨ¤
  • Now: āφāϧ⧁āύāĻŋāĻ• breadboard comes in āĻŦāĻŋāĻ­āĻŋāĻ¨ā§āύ size (170 tie-points mini, 400, 830 standard, āĻŦāĻĄāĻŧ size)āĨ¤

āĻŦāĻŋāĻ­āĻŋāĻ¨ā§āύ āϧāϰāύ⧇āϰ IC

ssss

will be added soon.


🧠 IC (Integrated Circuit) — Beginner theke Advanced (DLD Lab)Âļ

👀 Overview: IC āφāϏāϞ⧇ āϕ⧀, āϕ⧇āύ āĻĻāϰāĻ•āĻžāϰ, āϕ⧋āĻĨāĻžā§Ÿ āϞāĻžāϗ⧇Âļ

IC āĻŽāĻžāύ⧇ Integrated Circuit—āĻāĻ•āϟāĻž āϛ⧋āϟ āĻ•āĻžāϞ⧋ chip, āϭ⧇āϤāϰ⧇ āĻ…āύ⧇āĻ• transistor, resistor, capacitor āĻāĻ•āϏāĻžāĻĨ⧇ āĻ•āĻžāϜ āĻ•āϰ⧇āĨ¤
āϕ⧇āύ āĻĻāϰāĻ•āĻžāϰ: āĻāĻ•āχ āĻ•āĻžāĻœā§‡āϰ discrete parts āφāϞāĻžāĻĻāĻž āφāϞāĻžāĻĻāĻž āĻœā§‹ā§œāĻž āϞāĻžāĻ—āĻžāύ⧋āϰ āĻāĻžāĻŽā§‡āϞāĻž āĻ•āĻŽā§‡, size āϛ⧋āϟ āĻšā§Ÿ, speed āĻŦā§œā§‡, reliability āĻŦāĻžā§œā§‡āĨ¤
āϕ⧋āĻĨāĻžā§Ÿ āϞāĻžāϗ⧇: Digital Logic Lab (74xx gates), calculator, remote, toys, smartphone—āĻĒā§āϰāĻžā§Ÿ āϏāĻ°ā§āĻŦāĻ¤ā§āϰāĨ¤

Analogy

IC = āϛ⧋āϟ āĻāĻ•āϟāĻž āĻļāĻšāϰ đŸ™ī¸
āĻ­āĻŋāϤāϰ⧇ road, building, āĻŽāĻžāύ⧁āĻˇâ€”āϏāĻŦ āφāϛ⧇; āĻŦāĻžāχāϰ⧇ āϤ⧁āĻŽāĻŋ āĻļ⧁āϧ⧁ boundary (package) āφāϰ gate (pins) āĻĻ⧇āĻ–ā§‹āĨ¤
āϤ⧁āĻŽāĻŋ pins āĻĻāĻŋā§Ÿā§‡ āĻļāĻšāϰ⧇āϰ āϭ⧇āϤāϰ⧇āϰ āĻ…āĻ‚āĻļ⧇ message āĻĒāĻžāĻ āĻžāĻ“/āύāĻžāĻ“â€”āĻāϟāĻžāχ input/outputāĨ¤


🔤 Key Terms & SymbolsÂļ

  • Package: IC-āĻāϰ āĻŦāĻžāĻšāĻŋāϰ⧇āϰ āĻ•āĻ­āĻžāϰ (āϝ⧇āĻŽāύ DIP, SOIC, QFP, BGA)
  • Pin / Lead: āĻŦāĻžāĻšāĻŋāϰ⧇āϰ āϧāĻžāϤāĻŦ āĻĒāĻž, āϝ⧇āϗ⧁āϞ⧋ āĻĻāĻŋā§Ÿā§‡ connect āĻ•āϰāĻž āĻšā§Ÿ
  • Dot/Notch: Package-āĻ āϛ⧋āϟ āĻĻāĻžāĻ—/āĻ–āĻžāρāϜ → Pin‑1 āĻšā§‡āύāĻžāϰ āϚāĻŋāĻšā§āύ
  • Vcc/Vdd: Positive supply (DLD TTL-āĻ āϏāĻžāϧāĻžāϰāĻŖāϤ +5V)
  • GND/Vss: Ground/0V
  • TTL Family (74xx): āϏāĻžāϧāĻžāϰāĻŖāϤ +5V-āĻ āϚāϞ⧇
  • CMOS Family (40xx / 74HCxx): āϏāĻžāϧāĻžāϰāĻŖāϤ 3–15V compatible (model āĻ…āύ⧁āϝāĻžā§Ÿā§€)

🧩 Default / Initial Values (Lab Context)Âļ

Given/Assume (DLD lab-e prochur āĻŦā§āϝāĻŦāĻšā§ƒāϤ):

  • Supply (TTL 74LS/74HC): +5 V
  • Logic thresholds (TTL rough guide): LOW ≤ 0.8 V, HIGH â‰Ĩ 2.0 V
  • Decoupling capacitor: āĻĒā§āϰāϤāĻŋāϟāĻž IC-āĻāϰ supply pins-āĻāϰ āĻ•āĻžāϛ⧇ 0.1 ÂĩF (noise āĻ•āĻŽāĻžāϤ⧇)
  • Input bias: floating input āύāĻŋāώ⧇āϧ ❌ → pull-up/pull-down āϞāĻžāĻ—āĻŦ⧇ (≈ 10 kΊ āϏāĻžāϧāĻžāϰāĻŖ āϰ⧁āϞ)

āϛ⧋āϟ numeric āωāĻĻāĻžāĻšāϰāĻŖ (decoupling āϕ⧇āύ)

Supply line āĻ āϛ⧋āϟāĻ–āĻžāĻŸā§‹ voltage dip/spike āĻšāϞ⧇ IC glitch āĻ•āϰāϤ⧇ āĻĒāĻžāϰ⧇āĨ¤
0.1 ÂĩF cap āĻŽāĻŋāύāĻŋāϟāĻ–āĻžāύ⧇āϕ⧇āϰ āϜāĻ¨ā§āϝ āύāĻž, āĻ•āĻŋāĻ¨ā§āϤ⧁ microsecond-level spike smooth āĻ•āϰ⧇āĨ¤
āĻŦāĻžāĻ¸ā§āϤāĻŦ⧇: Vcc–GND across 0.1 ÂĩF āĻĻāĻŋāϞ⧇ random reset/garbage āĻ•āĻŽā§‡ ✅


🧱 Package & Pin Numbering (DIP āωāĻĻāĻžāĻšāϰāĻŖ)Âļ

and-gate-ic
- Notch/dot āĻ“āĻĒāϰ⧇ āϧāϰāϞ⧇ āĻŦāĻžāĻŽ āĻĻāĻŋāϕ⧇āϰ āωāĻĒāϰ⧇āϰ āĻĒāĻž = Pin‑1
- Anti‑clockwise āϘ⧁āϰ⧇ āύāĻŽā§āĻŦāϰ āĻŦāĻžā§œā§‡; 14‑pin-āĻ āϏāĻžāϧāĻžāϰāĻŖāϤ Pin‑14 = Vcc, Pin‑7 = GND

Orientation āϭ⧁āϞ āĻšāϞ⧇?

IC āωāĻ˛ā§āĻŸā§‹ āĻ•āϰāϞ⧇ Vcc/GND āĻĒāĻžāĻ˛ā§āĻŸā§‡ āĻ—āĻŋā§Ÿā§‡ chip damage āĻšāϤ⧇ āĻĒāĻžāϰ⧇ ❌
Power āĻĻ⧇āĻŦāĻžāϰ āφāϗ⧇ āĻĒāĻŋāĻ¨â€‘ā§§ āϚāĻŋāĻšā§āύ āĻĄāĻžāĻŦāĻ˛â€‘āĻšā§‡āĻ• āĻ•āϰ⧋āĨ¤


⚡ Logic Family Quick Summary (TTL vs CMOS)Âļ

Family Typical Vcc Pros Caution
74LS/74HC 5 V Lab‑friendly, easy availability Floating input āĻ āϭ⧁āϞ āφāϚāϰāĻŖ âš ī¸
4000‑series 3–15 V Wide voltage, low power āϧ⧀āϰ āĻšāϤ⧇ āĻĒāĻžāϰ⧇, model‑wise vary

Beginners’ Rule

DLD‑āĻ 74xx (5 V) āϧāϰ⧇āχ āĻļ⧁āϰ⧁ āĻ•āϰ⧋āĨ¤ āĻĒāϰ⧇ datasheet āĻĻ⧇āϖ⧇ exceptions āĻļāĻŋāĻ–āĻŦ⧇āĨ¤


đŸ§Ē Inside the ICÂļ

āĻ­āĻŋāϤāϰ⧇ āĻ…āύ⧇āĻ• transistor gate āĻŦāĻžāύāĻžā§Ÿ; gates āĻŽāĻŋāϞ⧇ functions (adder, counter) āĻŦāĻžāύāĻžā§Ÿ; āϏāĻŦ āĻāĻ• āϚāĻŋāĻĒ⧇ packed = integrationāĨ¤
VLSI āĻšāϞ⧇ millions/billions transistor—āϝ⧇āĻŽāύ smartphone SoCāĨ¤


đŸ—ēī¸ Tiny Timeline (Scale evolution)Âļ

  • SSI (1960s): āĻ•ā§Ÿā§‡āĻ•āϟāĻž gate
  • MSI (1970s): adder/counter‑type blocks
  • LSI (1980s): memory/controller
  • VLSI (1990s→): microprocessor/SoC (today’s billions)

Pin-1 āϏāύāĻžāĻ•ā§āϤāĻ•āϰāĻŖ

  • IC-āϤ⧇ āϏāĻŦāϏāĻŽā§Ÿ āϛ⧋āϟ āĻ–āĻžāρāϜ (notch) āĻŦāĻž āĻĄāϟ āĻĨāĻžāϕ⧇ Pin-1 āĻŦā§‹āĻāĻžāϰ āϜāĻ¨ā§āϝāĨ¤
  • āĻ–āĻžāρāϜ/āĻĄāϟ āωāĻĒāϰ⧇ āϰāĻžāĻ–āϞ⧇, āĻŦāĻžāĻŽ āĻĻāĻŋāϕ⧇āϰ āĻĒā§āϰāĻĨāĻŽ āĻĒāĻŋāύāχ Pin-1 ✅
  • āĻĒāĻŋāύ āĻ—ā§‹āύāĻž āĻšā§Ÿ counter-clockwise āĻĻāĻŋāϕ⧇āĨ¤
  • āϭ⧁āϞāĻ­āĻžāĻŦ⧇ āϧāϰāϞ⧇ VCC/GND āωāĻ˛ā§āĻŸā§‡ āĻ—āĻŋā§Ÿā§‡ IC āύāĻˇā§āϟ āĻšāϤ⧇ āĻĒāĻžāϰ⧇ âš ī¸

🔄 Flowchart: “āύāϤ⧁āύ IC āĻšāĻžāϤ⧇ āĻĒ⧇āϞ⧇ āϕ⧀āĻ­āĻžāĻŦ⧇ āĻļ⧁āϰ⧁ āĻ•āϰāĻŦā§‹?”Âļ

flowchart TD
    A["āύāϤ⧁āύ IC"] --> B["Pin-1 āϖ⧁āρāϜ⧁āύ (āĻĄāϟ/āύāϚ)"]
    B --> C["āĻĒā§āϝāĻžāϕ⧇āϜ/āĻĒāĻŋāύ āϏāĻ‚āĻ–ā§āϝāĻž āϝāĻžāϚāĻžāχ āĻ•āϰ⧁āύ"]
    C --> D["āĻĄāĻžāϟāĻžāĻļāĻŋāĻŸā§‡ VCC āϰ⧇āĻžā§āϜ āϝāĻžāϚāĻžāχ āĻ•āϰ⧁āύ"]
    D --> E["āĻĒāĻžāĻ“āϝāĻŧāĻžāϰ āĻĒāĻŋāύāϗ⧁āϞ⧋ āϚāĻŋāĻšā§āύāĻŋāϤ āĻ•āϰ⧁āύ (VCC/GND)"]
    E --> F["0.1 uF āĻĄāĻŋāĻ•āĻžāĻĒāϞāĻŋāĻ‚ āĻŦāϏāĻžāύ"]
    F --> G["I/O āϟāĻžāχāĻĒ āύāĻŋāĻ°ā§āϧāĻžāϰāĻŖ āĻ•āϰ⧁āύ (TTL/CMOS)"]
    G --> H{"āϕ⧋āύ⧋ āχāύāĻĒ⧁āϟ āĻĢā§āϞ⧋āϟāĻŋāĻ‚ āφāϛ⧇?"}
    H -- āĻšā§āϝāĻžāρ --> H1["~10k āĻĒ⧁āϞ āϰ⧇āϜāĻŋāĻ¸ā§āϟāϰ āϝ⧋āĻ— āĻ•āϰ⧁āύ"]
    H -- āύāĻž --> I["āĻ…āĻ—ā§āϰāϏāϰ āĻšā§‹āύ"]
    H1 --> I

🧾 Quick Summary TableÂļ

Topic Quick Note
Pin‑1 mark Dot/Notch
Counting direction Anti‑clockwise (top view)
Common power pins (DIP14) Pin‑14=Vcc, Pin‑7=GND
Floating inputs Avoid; use ~10 kΊ pull
Decoupling 0.1 ÂĩF across Vcc–GND
Family default 74xx → 5 V (lab)

âš ī¸ Common Mistakes & Quick FixÂļ

  • ❌ Pin‑1 āϭ⧁āϞ āϧāϰāĻž → ✅ Notch/dot confirm āĻ•āϰ⧋
  • ❌ Vcc/GND āĻŽāĻŋāĻ¸â€‘āĻ“ā§Ÿā§āϝāĻžāϰ → ✅ Power map āϞāĻŋāϖ⧇ āύāĻžāĻ“, āϤāĻžāϰāĻĒāϰ connect
  • ❌ Floating input → ✅ Pull‑up/pull‑down (~10 kΊ)
  • ❌ Decoupling āύāĻž āĻĻā§‡ā§ŸāĻž → ✅ 0.1 ÂĩF āĻĻāĻŋā§Ÿā§‡āχ āĻļ⧁āϰ⧁ āĻ•āϰ⧋
  • ❌ Mixed voltage family → ✅ āĻāĻ• voltage family maintain āĻ•āϰ⧋/level shift āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻ•āϰ⧋

🔁 RecapÂļ

IC = āϛ⧋āϟ āĻŦāĻ•ā§āϏ, āϭ⧇āϤāϰ⧇ āĻŦāĻŋāĻļāĻžāϞ āϏāĻžāĻ°ā§āĻ•āĻŋāϟāĨ¤ āĻļ⧁āϰ⧁āϤ⧇ āϝāĻž āĻŽāύ⧇ āϰāĻžāĻ–āĻŦ⧇: Pin‑1, Vcc/GND, family voltage, inputs fixed, decoupling—āĻāχāϗ⧁āϞ⧋ āĻ āĻŋāĻ• āĻĨāĻžāĻ•āϞ⧇ ⧝ā§Ļ% āĻāĻžāĻŽā§‡āϞāĻž āĻŦāĻ¨ā§āϧ ✅


🧩 Practice (āϛ⧋āϟ āĻĒā§āϰāĻļā§āύ, āĻāϟāĻĒāϟ āωāĻ¤ā§āϤāϰ)Âļ

1) Pin‑1 āĻšā§‡āύāĻžāϰ āϏāĻšāϜ āωāĻĒāĻžā§Ÿ āϕ⧀?
→ Dot/Notch āĻĻ⧇āĻ–ā§‹āĨ¤

2) 14‑pin 74xx‑āĻ Vcc/GND āϕ⧋āĻĨāĻžā§Ÿ āĻĨāĻžāϕ⧇?
→ Pin‑14 = Vcc, Pin‑7 = GND.

3) Floating input āϕ⧇āύ āĻ–āĻžāϰāĻžāĻĒ?
→ Random noise āϤ⧁āϞ⧇ unpredictable āφāϚāϰāĻŖ āĻ•āϰ⧇āĨ¤

4) Decoupling capacitor-āĻāϰ common value āĻ•āϤ āϰāĻžāĻ–āĻŦ⧇?
→ 0.1 ÂĩF (āĻĒā§āϰāϤāĻŋ IC‑āĻāϰ supply pins⧇āϰ āĻ•āĻžāϛ⧇)āĨ¤

5) TTL vs CMOS—āĻļ⧁āϰ⧁āϤ⧇ āϕ⧋āύāϟāĻž āϏāĻšāϜ?
→ Lab‑āĻ 74xx (TTL/HC) 5 V āĻĻāĻŋā§Ÿā§‡ āĻļ⧁āϰ⧁ āĻ•āϰāĻž āϏāĻšāϜāĨ¤

🧠 IC (Integrated Circuit) — DLD Lab NotesÂļ

OverviewÂļ

An Integrated Circuit is a compact chip containing many transistors/resistors/capacitors forming complete functions.
Why: smaller, faster, more reliable than discrete builds.
Where: 74xx logic labs, calculators, toys, phones, etc.

Key TermsÂļ

  • Package: external form (DIP, SOIC, QFP, BGA)
  • Pin/Lead: metal terminals to connect I/O and power
  • Dot/Notch: marks Pin‑1
  • Vcc/Vdd: positive supply (TTL lab: +5 V)
  • GND/Vss: ground/0 V
  • TTL (74xx): typically 5 V; CMOS (40xx/74HCxx): ~3–15 V (model‑dependent)

Defaults (Lab)Âļ

  • Supply: +5 V (74LS/74HC)
  • Logic thresholds (TTL guide): LOW ≤ 0.8 V, HIGH â‰Ĩ 2.0 V
  • Decoupling: 0.1 ÂĩF across Vcc–GND near each IC
  • Avoid floating inputs; use ~10 kΊ pull‑ups/downs

Package & Pin Numbering (DIP)Âļ

  • With dot/notch on top: top‑left = Pin‑1; count anti‑clockwise
  • 14‑pin common map: Pin‑14 = Vcc, Pin‑7 = GND

Family SnapshotÂļ

Family Vcc Pros Caution
74LS/74HC 5 V Lab‑friendly Define inputs; no float
4000 series 3–15 V Wide range, low power Slower; model dependent

Inside the IC (Idea)Âļ

Gates built from transistors; gates form functions; VLSI packs millions/billions (modern SoCs).

TimelineÂļ

SSI → MSI → LSI → VLSI (1960s → now).

Flowchart: First‑time IC SetupÂļ

flowchart TD
    A["New IC"] --> B["Find Pin-1 (dot/notch)"]
    B --> C["Check package/pin count"]
    C --> D["Verify VCC range in datasheet"]
    D --> E["Identify power pins (VCC/GND)"]
    E --> F["Place 0.1 uF decoupling"]
    F --> G["Classify I/O type (TTL/CMOS)"]
    G --> H{Any floating inputs?}
    H -- Yes --> H1["Add ~10k pull resistors"]
    H -- No --> I["Proceed"]
    H1 --> I

Quick SummaryÂļ

Topic Note
Pin‑1 marker Dot/Notch
Count direction Anti‑clockwise (top)
DIP‑14 power pins 14=Vcc, 7=GND
Floating inputs Avoid; add ~10 kΊ pull
Decoupling 0.1 ÂĩF near supply
Beginner family 74xx at 5 V

Common MistakesÂļ

Wrong orientation, miswired Vcc/GND, floating inputs, no decoupling, mixing families without level matching.

RecapÂļ

Learn the essentials first: Pin‑1, power pins, family voltage, stable inputs, decoupling. These remove most lab issues.

Practice (Short Answers)Âļ

1) How to find Pin‑1? Dot/Notch.
2) DIP‑14 power pins? 14=Vcc, 7=GND.
3) Why avoid floating inputs? Unpredictable behavior.
4) Typical decoupling value? 0.1 ÂĩF.
5) Beginner‑friendly family? 74xx at 5 V.