DLD - Lab BasicsÂļ
Breadboard
đą Part-1: Breadboard āĻā§?Âļ
Breadboard āĻšāϞ⧠āĻāĻāĻāĻž plastic board āϝā§āĻāĻžāϰ āĻŽāϧā§āϝ⧠āĻ
āύā§āĻāĻā§āϞ⧠āĻā§āĻ āĻā§āĻ hole (āĻāϰā§āϤ) āĻĨāĻžāĻā§āĨ¤
āĻāĻ hole-āĻā§āϞā§āϰ āĻāĻŋāϤāϰ⧠metal clips/strips āϞā§āĻāĻžāύ⧠āĻĨāĻžāĻā§ â āĻāĻā§āϞā§āĻ āύāĻŋāϰā§āĻĻāĻŋāώā§āĻāĻāĻžāĻŦā§ āĻāĻā§ āĻ
āĻĒāϰā§āϰ āϏāĻžāĻĨā§ connectedāĨ¤
đ āϤā§āĻŽāĻŋ āĻāĻāĻāĻž āϤāĻžāϰ (wire) āϝāĻĻāĻŋ āĻāĻāĻāĻž hole-āĻ āĻĸā§āĻāĻžāĻ āĻāϰ āĻāĻāĻ row-āĻāϰ āĻ āύā§āϝ hole-āĻ āĻĸā§āĻāĻžāĻ, āϏā§āĻāĻž āĻāĻāĻ āĻŦā§āĻĻā§āϝā§āϤāĻŋāĻ āϞāĻžāĻāύ (electrical connection) āĻšāĻŦā§āĨ¤
Analogy
Breadboard = āϏā§āĻā§āϞā§āϰ āĻŦā§āĻā§āĻ
- āĻŦā§āĻā§āĻā§ āĻĒāĻžāĻāĻāĻāύ āĻŦāĻžāĻā§āĻāĻž āĻĒāĻžāĻļāĻžāĻĒāĻžāĻļāĻŋ āĻŦāϏāϞ⧠āϤāĻžāϰāĻž āϏāĻŦāĻžāĻ āĻāĻ āĻŦā§āĻā§āĻā§ (connected)āĨ¤
- āĻāĻŋāύā§āϤ⧠āĻĒāĻžāĻļā§āϰ āĻŦā§āĻā§āĻā§ āĻŦāϏāĻž āĻŦāĻžāĻā§āĻāĻžāĻĻā§āϰ āϏāĻžāĻĨā§ āϤāĻžāĻĻā§āϰ direct connection āύā§āĻ âāĨ¤
đ§Š Part-2: āĻāĻŋāϤāϰā§āϰ Connection SecretÂļ
⥠Breadboard āĻāϏāϞ⧠āĻāĻŋāϤāϰ⧠āĻā§āĻāĻžāĻŦā§ connected?Âļ

Breadboard āĻāϰ holes āĻā§āϞ⧠āϏāĻŦ āĻāϞāĻžāĻĻāĻž āύāĻžāĨ¤ āĻā§āϤāϰ⧠hidden metal strips āĻāĻā§āĨ¤
-
āĻŽāĻžāĻāĻāĻžāύā§:
-
āĻāĻ row-āĻāϰ AâE āĻāĻāϏāĻžāĻĨā§ connected â
- āĻāĻāĻ row-āĻāϰ FâJ āĻāĻāϏāĻžāĻĨā§ connected â
- āĻāĻŋāύā§āϤ⧠AâE āĻāϰ FâJ āĻāĻā§ āĻ āĻĒāϰā§āϰ āϏāĻžāĻĨā§ connected āύāĻž â
-
āĻŽāĻžāĻāĻāĻžāύā§āϰ gap āĻāĻž āĻāϏāϞ⧠IC āĻŦāϏāĻžāύā§āϰ āĻāĻžā§āĻāĻžāĨ¤
-
āĻĒāĻžāĻļā§: āϞāĻŽā§āĻŦāĻž āĻĻā§āĻāĻāĻž line āĻĨāĻžāĻā§ (Power rail)
-
āϞāĻžāϞ ( + ) â Vcc (+5V)
- āύā§āϞ/āĻāĻžāϞ⧠( â ) â GND (0V)
đ Quick Table (Who connects to whom?)Âļ
| Section | Connection Rule |
|---|---|
| AâE row | āĻāĻā§ āĻ āĻĒāϰā§āϰ āϏāĻžāĻĨā§ shorted (internal metal strip) â |
| FâJ row | āĻāĻā§ āĻ āĻĒāϰā§āϰ āϏāĻžāĻĨā§ shorted â |
| Gap | Left vs Right side NOT connected â |
| Power Rail + | āϏāĻŦ āϞāĻžāϞ hole āϏāĻžāϧāĻžāϰāĻŖāϤ connected (āĻāĻāύ⧠āĻŽāĻžāĻāĻāĻžāύ⧠break â ī¸) |
| Power Rail â | āϏāĻŦ āύā§āϞ hole āϏāĻžāϧāĻžāϰāĻŖāϤ connected |
Part-4: Breadboard āĻāϰ Evolution / TimelineÂļ
- 1940s: Wooden breadboard-āĻ actual nails āĻĻāĻŋāϝāĻŧā§ circuit āĻŦāĻžāύāĻžāύ⧠āĻšāϤā§āĨ¤
- 1970s: Plastic solderless breadboard āĻāĻĻā§āĻāĻžāĻŦāĻŋāϤ āĻšāϝāĻŧāĨ¤
- Now: āĻāϧā§āύāĻŋāĻ breadboard comes in āĻŦāĻŋāĻāĻŋāύā§āύ size (170 tie-points mini, 400, 830 standard, āĻŦāĻĄāĻŧ size)āĨ¤
āĻŦāĻŋāĻāĻŋāύā§āύ āϧāϰāύā§āϰ IC
ssss
will be added soon.
đ§ IC (Integrated Circuit) â Beginner theke Advanced (DLD Lab)Âļ
đ Overview: IC āĻāϏāϞ⧠āĻā§, āĻā§āύ āĻĻāϰāĻāĻžāϰ, āĻā§āĻĨāĻžā§ āϞāĻžāĻā§Âļ
IC āĻŽāĻžāύ⧠Integrated CircuitâāĻāĻāĻāĻž āĻā§āĻ āĻāĻžāϞ⧠chip, āĻā§āϤāϰ⧠āĻ
āύā§āĻ transistor, resistor, capacitor āĻāĻāϏāĻžāĻĨā§ āĻāĻžāĻ āĻāϰā§āĨ¤
āĻā§āύ āĻĻāϰāĻāĻžāϰ: āĻāĻāĻ āĻāĻžāĻā§āϰ discrete parts āĻāϞāĻžāĻĻāĻž āĻāϞāĻžāĻĻāĻž āĻā§ā§āĻž āϞāĻžāĻāĻžāύā§āϰ āĻāĻžāĻŽā§āϞāĻž āĻāĻŽā§, size āĻā§āĻ āĻšā§, speed āĻŦā§ā§, reliability āĻŦāĻžā§ā§āĨ¤
āĻā§āĻĨāĻžā§ āϞāĻžāĻā§: Digital Logic Lab (74xx gates), calculator, remote, toys, smartphoneâāĻĒā§āϰāĻžā§ āϏāϰā§āĻŦāϤā§āϰāĨ¤
Analogy
IC = āĻā§āĻ āĻāĻāĻāĻž āĻļāĻšāϰ đī¸
āĻāĻŋāϤāϰ⧠road, building, āĻŽāĻžāύā§āώâāϏāĻŦ āĻāĻā§; āĻŦāĻžāĻāϰ⧠āϤā§āĻŽāĻŋ āĻļā§āϧ⧠boundary (package) āĻāϰ gate (pins) āĻĻā§āĻā§āĨ¤
āϤā§āĻŽāĻŋ pins āĻĻāĻŋā§ā§ āĻļāĻšāϰā§āϰ āĻā§āϤāϰā§āϰ āĻ
āĻāĻļā§ message āĻĒāĻžāĻ āĻžāĻ/āύāĻžāĻâāĻāĻāĻžāĻ input/outputāĨ¤
đ¤ Key Terms & SymbolsÂļ
- Package: IC-āĻāϰ āĻŦāĻžāĻšāĻŋāϰā§āϰ āĻāĻāĻžāϰ (āϝā§āĻŽāύ DIP, SOIC, QFP, BGA)
- Pin / Lead: āĻŦāĻžāĻšāĻŋāϰā§āϰ āϧāĻžāϤāĻŦ āĻĒāĻž, āϝā§āĻā§āϞ⧠āĻĻāĻŋā§ā§ connect āĻāϰāĻž āĻšā§
- Dot/Notch: Package-āĻ āĻā§āĻ āĻĻāĻžāĻ/āĻāĻžāĻāĻ â Pinâ1 āĻā§āύāĻžāϰ āĻāĻŋāĻšā§āύ
- Vcc/Vdd: Positive supply (DLD TTL-āĻ āϏāĻžāϧāĻžāϰāĻŖāϤ +5V)
- GND/Vss: Ground/0V
- TTL Family (74xx): āϏāĻžāϧāĻžāϰāĻŖāϤ +5V-āĻ āĻāϞā§
- CMOS Family (40xx / 74HCxx): āϏāĻžāϧāĻžāϰāĻŖāϤ 3â15V compatible (model āĻ āύā§āϝāĻžā§ā§)
đ§Š Default / Initial Values (Lab Context)Âļ
Given/Assume (DLD lab-e prochur āĻŦā§āϝāĻŦāĻšā§āϤ):
- Supply (TTL 74LS/74HC): +5â¯V
- Logic thresholds (TTL rough guide): LOW ⤠0.8â¯V, HIGH âĨ 2.0â¯V
- Decoupling capacitor: āĻĒā§āϰāϤāĻŋāĻāĻž IC-āĻāϰ supply pins-āĻāϰ āĻāĻžāĻā§ 0.1â¯ÂĩF (noise āĻāĻŽāĻžāϤā§)
- Input bias: floating input āύāĻŋāώā§āϧ â â pull-up/pull-down āϞāĻžāĻāĻŦā§ (â 10â¯kΊ āϏāĻžāϧāĻžāϰāĻŖ āϰā§āϞ)
āĻā§āĻ numeric āĻāĻĻāĻžāĻšāϰāĻŖ (decoupling āĻā§āύ)
Supply line āĻ āĻā§āĻāĻāĻžāĻā§ voltage dip/spike āĻšāϞ⧠IC glitch āĻāϰāϤ⧠āĻĒāĻžāϰā§āĨ¤
0.1â¯ÂĩF cap āĻŽāĻŋāύāĻŋāĻāĻāĻžāύā§āĻā§āϰ āĻāύā§āϝ āύāĻž, āĻāĻŋāύā§āϤ⧠microsecond-level spike smooth āĻāϰā§āĨ¤
āĻŦāĻžāϏā§āϤāĻŦā§: VccâGND across 0.1â¯ÂĩF āĻĻāĻŋāϞ⧠random reset/garbage āĻāĻŽā§ â
đ§ą Package & Pin Numbering (DIP āĻāĻĻāĻžāĻšāϰāĻŖ)Âļ

- Notch/dot āĻāĻĒāϰ⧠āϧāϰāϞ⧠āĻŦāĻžāĻŽ āĻĻāĻŋāĻā§āϰ āĻāĻĒāϰā§āϰ āĻĒāĻž = Pinâ1
- Antiâclockwise āĻā§āϰ⧠āύāĻŽā§āĻŦāϰ āĻŦāĻžā§ā§; 14âpin-āĻ āϏāĻžāϧāĻžāϰāĻŖāϤ Pinâ14 = Vcc, Pinâ7 = GND
Orientation āĻā§āϞ āĻšāϞā§?
IC āĻāϞā§āĻā§ āĻāϰāϞ⧠Vcc/GND āĻĒāĻžāϞā§āĻā§ āĻāĻŋā§ā§ chip damage āĻšāϤ⧠āĻĒāĻžāϰ⧠â
Power āĻĻā§āĻŦāĻžāϰ āĻāĻā§ āĻĒāĻŋāύâā§§ āĻāĻŋāĻšā§āύ āĻĄāĻžāĻŦāϞâāĻā§āĻ āĻāϰā§āĨ¤
⥠Logic Family Quick Summary (TTL vs CMOS)Âļ
| Family | Typical Vcc | Pros | Caution |
|---|---|---|---|
| 74LS/74HC | 5â¯V | Labâfriendly, easy availability | Floating input āĻ āĻā§āϞ āĻāĻāϰāĻŖ â ī¸ |
| 4000âseries | 3â15â¯V | Wide voltage, low power | āϧā§āϰ āĻšāϤ⧠āĻĒāĻžāϰā§, modelâwise vary |
Beginnersâ Rule
DLDâāĻ 74xx (5â¯V) āϧāϰā§āĻ āĻļā§āϰ⧠āĻāϰā§āĨ¤ āĻĒāϰ⧠datasheet āĻĻā§āĻā§ exceptions āĻļāĻŋāĻāĻŦā§āĨ¤
đ§Ē Inside the ICÂļ
āĻāĻŋāϤāϰ⧠āĻ
āύā§āĻ transistor gate āĻŦāĻžāύāĻžā§; gates āĻŽāĻŋāϞ⧠functions (adder, counter) āĻŦāĻžāύāĻžā§; āϏāĻŦ āĻāĻ āĻāĻŋāĻĒā§ packed = integrationāĨ¤
VLSI āĻšāϞ⧠millions/billions transistorâāϝā§āĻŽāύ smartphone SoCāĨ¤
đēī¸ Tiny Timeline (Scale evolution)Âļ
- SSI (1960s): āĻā§ā§āĻāĻāĻž gate
- MSI (1970s): adder/counterâtype blocks
- LSI (1980s): memory/controller
- VLSI (1990sâ): microprocessor/SoC (todayâs billions)
Pin-1 āϏāύāĻžāĻā§āϤāĻāϰāĻŖ
- IC-āϤ⧠āϏāĻŦāϏāĻŽā§ āĻā§āĻ āĻāĻžāĻāĻ (notch) āĻŦāĻž āĻĄāĻ āĻĨāĻžāĻā§ Pin-1 āĻŦā§āĻāĻžāϰ āĻāύā§āϝāĨ¤
- āĻāĻžāĻāĻ/āĻĄāĻ āĻāĻĒāϰ⧠āϰāĻžāĻāϞā§, āĻŦāĻžāĻŽ āĻĻāĻŋāĻā§āϰ āĻĒā§āϰāĻĨāĻŽ āĻĒāĻŋāύāĻ Pin-1 â
- āĻĒāĻŋāύ āĻā§āύāĻž āĻšā§ counter-clockwise āĻĻāĻŋāĻā§āĨ¤
- āĻā§āϞāĻāĻžāĻŦā§ āϧāϰāϞ⧠VCC/GND āĻāϞā§āĻā§ āĻāĻŋā§ā§ IC āύāώā§āĻ āĻšāϤ⧠āĻĒāĻžāϰ⧠â ī¸
đ Flowchart: âāύāϤā§āύ IC āĻšāĻžāϤ⧠āĻĒā§āϞ⧠āĻā§āĻāĻžāĻŦā§ āĻļā§āϰ⧠āĻāϰāĻŦā§?âÂļ
flowchart TD
A["āύāϤā§āύ IC"] --> B["Pin-1 āĻā§āĻāĻā§āύ (āĻĄāĻ/āύāĻ)"]
B --> C["āĻĒā§āϝāĻžāĻā§āĻ/āĻĒāĻŋāύ āϏāĻāĻā§āϝāĻž āϝāĻžāĻāĻžāĻ āĻāϰā§āύ"]
C --> D["āĻĄāĻžāĻāĻžāĻļāĻŋāĻā§ VCC āϰā§āĻā§āĻ āϝāĻžāĻāĻžāĻ āĻāϰā§āύ"]
D --> E["āĻĒāĻžāĻāϝāĻŧāĻžāϰ āĻĒāĻŋāύāĻā§āϞ⧠āĻāĻŋāĻšā§āύāĻŋāϤ āĻāϰā§āύ (VCC/GND)"]
E --> F["0.1 uF āĻĄāĻŋāĻāĻžāĻĒāϞāĻŋāĻ āĻŦāϏāĻžāύ"]
F --> G["I/O āĻāĻžāĻāĻĒ āύāĻŋāϰā§āϧāĻžāϰāĻŖ āĻāϰā§āύ (TTL/CMOS)"]
G --> H{"āĻā§āύ⧠āĻāύāĻĒā§āĻ āĻĢā§āϞā§āĻāĻŋāĻ āĻāĻā§?"}
H -- āĻšā§āϝāĻžāĻ --> H1["~10k āĻĒā§āϞ āϰā§āĻāĻŋāϏā§āĻāϰ āϝā§āĻ āĻāϰā§āύ"]
H -- āύāĻž --> I["āĻ
āĻā§āϰāϏāϰ āĻšā§āύ"]
H1 --> I
đ§ž Quick Summary TableÂļ
| Topic | Quick Note |
|---|---|
| Pinâ1 mark | Dot/Notch |
| Counting direction | Antiâclockwise (top view) |
| Common power pins (DIP14) | Pinâ14=Vcc, Pinâ7=GND |
| Floating inputs | Avoid; use ~10â¯kΊ pull |
| Decoupling | 0.1â¯ÂĩF across VccâGND |
| Family default | 74xx â 5â¯V (lab) |
â ī¸ Common Mistakes & Quick FixÂļ
- â Pinâ1 āĻā§āϞ āϧāϰāĻž â â Notch/dot confirm āĻāϰā§
- â Vcc/GND āĻŽāĻŋāϏâāĻā§ā§āϝāĻžāϰ â â Power map āϞāĻŋāĻā§ āύāĻžāĻ, āϤāĻžāϰāĻĒāϰ connect
- â Floating input â â Pullâup/pullâdown (~10â¯kΊ)
- â Decoupling āύāĻž āĻĻā§ā§āĻž â â 0.1â¯ÂĩF āĻĻāĻŋā§ā§āĻ āĻļā§āϰ⧠āĻāϰā§
- â Mixed voltage family â â āĻāĻ voltage family maintain āĻāϰā§/level shift āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻāϰā§
đ RecapÂļ
IC = āĻā§āĻ āĻŦāĻā§āϏ, āĻā§āϤāϰ⧠āĻŦāĻŋāĻļāĻžāϞ āϏāĻžāϰā§āĻāĻŋāĻāĨ¤ āĻļā§āϰā§āϤ⧠āϝāĻž āĻŽāύ⧠āϰāĻžāĻāĻŦā§: Pinâ1, Vcc/GND, family voltage, inputs fixed, decouplingâāĻāĻāĻā§āϞ⧠āĻ āĻŋāĻ āĻĨāĻžāĻāϞ⧠⧝ā§Ļ% āĻāĻžāĻŽā§āϞāĻž āĻŦāύā§āϧ â
đ§Š Practice (āĻā§āĻ āĻĒā§āϰāĻļā§āύ, āĻāĻāĻĒāĻ āĻāϤā§āϤāϰ)Âļ
1) Pinâ1 āĻā§āύāĻžāϰ āϏāĻšāĻ āĻāĻĒāĻžā§ āĻā§?
â Dot/Notch āĻĻā§āĻā§āĨ¤
2) 14âpin 74xxâāĻ Vcc/GND āĻā§āĻĨāĻžā§ āĻĨāĻžāĻā§?
â Pinâ14 = Vcc, Pinâ7 = GND.
3) Floating input āĻā§āύ āĻāĻžāϰāĻžāĻĒ?
â Random noise āϤā§āϞ⧠unpredictable āĻāĻāϰāĻŖ āĻāϰā§āĨ¤
4) Decoupling capacitor-āĻāϰ common value āĻāϤ āϰāĻžāĻāĻŦā§?
â 0.1â¯ÂĩF (āĻĒā§āϰāϤāĻŋ ICâāĻāϰ supply pinsā§āϰ āĻāĻžāĻā§)āĨ¤
5) TTL vs CMOSâāĻļā§āϰā§āϤ⧠āĻā§āύāĻāĻž āϏāĻšāĻ?
â LabâāĻ 74xx (TTL/HC) 5â¯V āĻĻāĻŋā§ā§ āĻļā§āϰ⧠āĻāϰāĻž āϏāĻšāĻāĨ¤
đ§ IC (Integrated Circuit) â DLD Lab NotesÂļ
OverviewÂļ
An Integrated Circuit is a compact chip containing many transistors/resistors/capacitors forming complete functions.
Why: smaller, faster, more reliable than discrete builds.
Where: 74xx logic labs, calculators, toys, phones, etc.
Key TermsÂļ
- Package: external form (DIP, SOIC, QFP, BGA)
- Pin/Lead: metal terminals to connect I/O and power
- Dot/Notch: marks Pinâ1
- Vcc/Vdd: positive supply (TTL lab: +5â¯V)
- GND/Vss: ground/0â¯V
- TTL (74xx): typically 5â¯V; CMOS (40xx/74HCxx): ~3â15â¯V (modelâdependent)
Defaults (Lab)Âļ
- Supply: +5â¯V (74LS/74HC)
- Logic thresholds (TTL guide): LOW ⤠0.8â¯V, HIGH âĨ 2.0â¯V
- Decoupling: 0.1â¯ÂĩF across VccâGND near each IC
- Avoid floating inputs; use ~10â¯kΊ pullâups/downs
Package & Pin Numbering (DIP)Âļ
- With dot/notch on top: topâleft = Pinâ1; count antiâclockwise
- 14âpin common map: Pinâ14 = Vcc, Pinâ7 = GND
Family SnapshotÂļ
| Family | Vcc | Pros | Caution |
|---|---|---|---|
| 74LS/74HC | 5â¯V | Labâfriendly | Define inputs; no float |
| 4000 series | 3â15â¯V | Wide range, low power | Slower; model dependent |
Inside the IC (Idea)Âļ
Gates built from transistors; gates form functions; VLSI packs millions/billions (modern SoCs).
TimelineÂļ
SSI â MSI â LSI â VLSI (1960s â now).
Flowchart: Firstâtime IC SetupÂļ
flowchart TD
A["New IC"] --> B["Find Pin-1 (dot/notch)"]
B --> C["Check package/pin count"]
C --> D["Verify VCC range in datasheet"]
D --> E["Identify power pins (VCC/GND)"]
E --> F["Place 0.1 uF decoupling"]
F --> G["Classify I/O type (TTL/CMOS)"]
G --> H{Any floating inputs?}
H -- Yes --> H1["Add ~10k pull resistors"]
H -- No --> I["Proceed"]
H1 --> I
Quick SummaryÂļ
| Topic | Note |
|---|---|
| Pinâ1 marker | Dot/Notch |
| Count direction | Antiâclockwise (top) |
| DIPâ14 power pins | 14=Vcc, 7=GND |
| Floating inputs | Avoid; add ~10â¯kΊ pull |
| Decoupling | 0.1â¯ÂĩF near supply |
| Beginner family | 74xx at 5â¯V |
Common MistakesÂļ
Wrong orientation, miswired Vcc/GND, floating inputs, no decoupling, mixing families without level matching.
RecapÂļ
Learn the essentials first: Pinâ1, power pins, family voltage, stable inputs, decoupling. These remove most lab issues.
Practice (Short Answers)Âļ
1) How to find Pinâ1? Dot/Notch.
2) DIPâ14 power pins? 14=Vcc, 7=GND.
3) Why avoid floating inputs? Unpredictable behavior.
4) Typical decoupling value? 0.1â¯ÂĩF.
5) Beginnerâfriendly family? 74xx at 5â¯V.
