Skip to content

XNOR Gate from NAND Gate

Implementation of XNOR Gate from NAND GateÂļ

āφāĻŽāϰāĻž āϜāĻžāύāĻŋ, NAND Gate āĻšāϞ⧋ āĻāĻ•āϟāĻŋ universal logic gate, āϝ⧇āϟāĻŋ āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻ•āϰ⧇ āϝ⧇āϕ⧋āύ⧋ āϧāϰāύ⧇āϰ logic gate āϤ⧈āϰāĻŋ āĻ•āϰāĻž āϝāĻžā§ŸāĨ¤ āĻāĻ–āύ āφāĻŽāϰāĻž āϕ⧇āĻŦāϞ NAND gate āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻ•āϰ⧇ XNOR gate āĻŦāĻžāĻ¸ā§āϤāĻŦāĻžā§Ÿāύ āĻ•āϰāĻŦāĨ¤

image-47.png

Full AND/OR/NOT Set to Implement Ex-NOR

What is a XNOR Gate?Âļ

XNOR (Exclusive-NOR) Gate āĻšāϞ⧋ āĻāĻ•āϟāĻŋ derived logic gateāĨ¤ āĻāϰ āĻĻ⧁āϟāĻŋ āχāύāĻĒ⧁āϟ āĻāĻŦāĻ‚ āĻāĻ•āϟāĻŋ āφāωāϟāĻĒ⧁āϟ āĻĨāĻžāϕ⧇āĨ¤ XNOR gate āϤāĻ–āύāχ HIGH (Logic 1) āφāωāϟāĻĒ⧁āϟ āĻĻā§‡ā§Ÿ āϝāĻ–āύ āĻĻ⧁āϟāĻŋ āχāύāĻĒ⧁āϟ āϏāĻŽāĻžāύ āĻĨāĻžāϕ⧇ (āωāϭ⧟āχ 0 āĻ…āĻĨāĻŦāĻž āωāϭ⧟āχ 1)āĨ¤ āĻ•āĻŋāĻ¨ā§āϤ⧁ āϝāĻ–āύ āĻĻ⧁āϟāĻŋ āχāύāĻĒ⧁āϟ āφāϞāĻžāĻĻāĻž āĻĨāĻžāϕ⧇, āϤāĻ–āύ āφāωāϟāĻĒ⧁āϟ LOW (Logic 0) āĻšā§ŸāĨ¤

Figure 1 - XNOR Gate

Output Equation of XNOR GateÂļ

\[ Y = \overline{(A \oplus B)} = AB + \overline{A}\,\overline{B} \]

Truth Table of XNOR GateÂļ

A B Output ($Y = \overline{(A \oplus B)}$)
0 0 1
0 1 0
1 0 0
1 1 1

What is a NAND Gate?Âļ

NAND Gate āĻšāϞ⧋ āĻāĻ•āϟāĻŋ universal logic gateāĨ¤ āĻāϟāĻŋ āĻŽā§‚āϞāϤ AND āĻāĻŦāĻ‚ NOT gate-āĻāϰ āϏāĻŽāĻ¨ā§āĻŦ⧟āĨ¤ NAND gate-āĻāϰ āφāωāϟāĻĒ⧁āϟ LOW āĻšā§Ÿ āϤāĻ–āύāχ āϝāĻ–āύ āĻāϰ āϏāĻŦ āχāύāĻĒ⧁āϟ HIGH āĻšā§Ÿ, āĻŦāĻžāĻ•āĻŋ āϏāĻŦ āĻ•ā§āώ⧇āĻ¤ā§āϰ⧇ āφāωāϟāĻĒ⧁āϟ HIGH āĻĨāĻžāϕ⧇āĨ¤
NAND Gate

Output Equation of NAND GateÂļ

\[ Y = \overline{(A \cdot B)} \]

Truth Table of NAND GateÂļ

A B Output ($Y = \overline{(A \cdot B)}$)
0 0 1
0 1 1
1 0 1
1 1 0

Implementation of XNOR Gate from NAND GateÂļ

alt text
Figure-3-āĻ ā§ĢāϟāĻŋ NAND gate āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻ•āϰ⧇ āĻāĻ•āϟāĻŋ XNOR gate āĻāϰ āĻŦāĻžāĻ¸ā§āϤāĻŦāĻžā§Ÿāύ āĻĻ⧇āĻ–āĻžāύ⧋ āĻšā§Ÿā§‡āϛ⧇āĨ¤

āĻāĻ–āύ āϧāĻžāĻĒ⧇ āϧāĻžāĻĒ⧇ āĻĻ⧇āĻ–āĻŋ āϕ⧀āĻ­āĻžāĻŦ⧇ āĻāχ āϏāĻžāĻ°ā§āĻ•āĻŋāϟ āĻ•āĻžāϜ āĻ•āϰ⧇āĨ¤

āĻĒā§āϰāĻĨāĻŽ NAND gate-āĻāϰ āφāωāϟāĻĒ⧁āϟāσ

\[ Y_1 = \overline{(A \cdot B)} \]

āĻĻā§āĻŦāĻŋāĻ¤ā§€ā§Ÿ NAND gate-āĻāϰ āφāωāϟāĻĒ⧁āϟāσ

\[ Y_2 = \overline{(A \cdot Y_1)} = \overline{(A \cdot \overline{(A \cdot B)})} \]

āϤ⧃āĻ¤ā§€ā§Ÿ NAND gate-āĻāϰ āφāωāϟāĻĒ⧁āϟāσ

\[ Y_3 = \overline{(B \cdot Y_1)} = \overline{(B \cdot \overline{(A \cdot B)})} \]

āϚāϤ⧁āĻ°ā§āĻĨ NAND gate-āĻāϰ āφāωāϟāĻĒ⧁āϟāσ

\[ Y_4 = \overline{(Y_2 \cdot Y_3)} \]

āĻĒāĻžā§āϚāĻŽ NAND gate-āĻ $Y_1$ āĻāĻŦāĻ‚ $Y_4$ āĻĻāĻŋāϞ⧇ āĻĒāĻžāĻ“ā§ŸāĻž āϝāĻžā§Ÿāσ

\[ Y = \overline{(Y_1 \cdot Y_4)} \]

āĻāĻ–āύ expand āĻ•āϰāϞ⧇:

⇒ \(Y = AB + \overline{A}\,\overline{B}\)

⇒ \(Y = \overline{(A \oplus B)}\)


IC Implementation of the XNOR using NAND:Âļ

IC Implementation of the XNOR using NAND

Testing:Âļ

se

✅ āĻāχāĻ­āĻžāĻŦ⧇ āĻļ⧁āϧ⧁āĻŽāĻžāĻ¤ā§āϰ NAND gate āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻ•āϰ⧇āĻ“ āĻāĻ•āϟāĻŋ XNOR gate āϤ⧈āϰāĻŋ āĻ•āϰāĻž āϏāĻŽā§āĻ­āĻŦāĨ¤

āϏāĻ‚āĻ•ā§āώ⧇āĻĒ⧇ āĻŽāύ⧇ āϰāĻžāĻ–ā§‹āσ

  • A ⊕ B → XOR gate
  • A ⊙ B → XNOR gate

āφāϰ bar āĻĻāĻŋāϞ⧇ →

\(\overline{A \oplus B}\) = \(A ⊙ B\)

āĻŽāĻžāύ⧇, XOR-āĻāϰ āωāĻĒāϰ wholebar = XNORāĨ¤