Index
đģ āĻāĻŽā§āĻĒāĻŋāĻāĻāĻžāϰ āĻāϏāϞ⧠āĻā§? (The Basics)Âļ
đ§ āĻāύā§āĻā§āϰā§āϞ āĻāĻāύāĻŋāĻ (The Manager)Âļ
āϏāĻŦāĻāĻŋāĻā§āϰ āĻŽā§āϞ āĻāĻžāϞāĻŋāĻāĻžāĻļāĻā§āϤāĻŋ āĻšāϞ⧠Control Unit (CU)āĨ¤ āĻāĻāĻŋ CPU-āĻāϰ āĻā§āϤāϰ⧠āĻĨāĻžāĻā§ āĻāĻŦāĻ āĻĒā§āϰ⧠āĻāĻžāĻāĻāĻŋāĻā§ āĻĻā§āĻāĻŋ āĻĒā§āϰāϧāĻžāύ āĻāĻžāĻā§ āĻāĻžāĻ āĻāϰā§:
- Instruction Interpretation (āĻŦā§āϝāĻžāĻā§āϝāĻžāĻāϰāĻŖ): āĻĒā§āϰāĻĨāĻŽā§ āĻāύā§āĻā§āϰā§āϞ āĻāĻāύāĻŋāĻ āĻŽā§āĻŽā§āϰāĻŋ āĻĨā§āĻā§ āĻāĻāĻāĻŋ āĻāύāϏā§āĻā§āϰāĻžāĻāĻļāύ āĻĒā§ā§ āĻāĻŦāĻ āĻŦā§āĻāĻžāϰ āĻā§āώā§āĻāĻž āĻāϰ⧠āϝ⧠āĻāĻāĻŋ āĻāϏāϞ⧠āĻā§ āĻāϰāϤ⧠āĻŦāϞāĻž āĻšā§ā§āĻā§ (āϝā§āĻŽāύ: āϝā§āĻ āύāĻžāĻāĻŋ āĻŦāĻŋāϝāĻŧā§āĻ)āĨ¤ āĻāϰāĻĒāϰ āϏ⧠āĻĒā§āϰā§ā§āĻāύā§ā§ āĻĄā§āĻāĻž āϏāĻāĻā§āϰāĻš āĻāϰ⧠ALU (Arithmetic Logic Unit)-āĻā§ āĻāĻžāĻ āĻļā§āϰ⧠āĻāϰāĻžāϰ āϏāĻŋāĻāύā§āϝāĻžāϞ āĻĻā§ā§āĨ¤
- Instruction Sequencing (āĻā§āϰāĻŽ āύāĻŋāϰā§āϧāĻžāϰāĻŖ): āϏāĻžāϧāĻžāϰāĻŖāϤ āĻāĻŽā§āĻĒāĻŋāĻāĻāĻžāϰ āĻāĻāĻāĻžāϰ āĻĒāϰ āĻāĻāĻāĻž āĻāύāϏā§āĻā§āϰāĻžāĻāĻļāύ āϏāĻŋāϰāĻŋā§āĻžāϞāĻŋ āĻĒāĻžāϞāύ āĻāϰā§āĨ¤ āĻāύā§āĻā§āϰā§āϞ āĻāĻāύāĻŋāĻ āĻ āĻŋāĻ āĻāϰ⧠āĻĻā§ā§ āĻĒāϰāĻŦāϰā§āϤ⧠āĻā§āύ āĻāĻžāĻāĻāĻŋ āĻāϰāϤ⧠āĻšāĻŦā§āĨ¤
đ āĻŦā§āϝāϤāĻŋāĻā§āϰāĻŽā§ āĻĒāϰāĻŋāϏā§āĻĨāĻŋāϤāĻŋ (Exceptions to the Rule)Âļ
āϏāĻŦāϏāĻŽā§ āϝ⧠āĻāĻŽā§āĻĒāĻŋāĻāĻāĻžāϰ āϏā§āĻāĻž āĻĒāĻĨā§ āĻāϞ⧠āϤāĻž āύā§āĨ¤ āĻŽāĻžāĻā§ āĻŽāĻžāĻā§ āϤāĻžāĻā§ āϞāĻžāĻāύ āĻĨā§āĻā§ āĻŦāĻŋāĻā§āϝā§āϤ āĻšāϤ⧠āĻšā§āĨ¤ āĻāĻĒāύāĻžāϰ āĻāĻŦāĻŋāϤ⧠āĻĻā§āĻāĻŋ āĻĒā§āϰāϧāĻžāύ āĻĒāϰāĻŋāϏā§āĻĨāĻŋāϤāĻŋāϰ āĻāĻĨāĻž āĻŦāϞāĻž āĻšā§ā§āĻā§:
- Branch Instruction (āĻŦā§āϰāĻžāĻā§āĻāĻŋāĻ): āϝāĻāύ āĻāĻŽā§āĻĒāĻŋāĻāĻāĻžāϰāĻā§ āĻŦāϞāĻž āĻšā§ āϏā§āĻāĻž āύāĻž āĻāĻŋā§ā§ āĻ āύā§āϝ āĻā§āύ⧠āĻ ā§āϝāĻžāĻĄā§āϰā§āϏ⧠(āϧāϰāĻž āϝāĻžāĻ Address B) āϞāĻžāĻĢ āĻĻāĻŋā§ā§ āĻāϞ⧠āϝā§āϤā§āĨ¤
- Subroutine Calls (āϏāĻžāĻŦāϰā§āĻāĻŋāύ): āϝāĻāύ āĻŽā§āϞ āĻĒā§āϰā§āĻā§āϰāĻžāĻŽ āĻĨāĻžāĻŽāĻŋā§ā§ āĻā§āĻ āĻāĻāĻāĻŋ āĻāĻĒ-āĻĒā§āϰā§āĻā§āϰāĻžāĻŽ (Subprogram) āĻāĻžāϞāĻžāύ⧠āĻšā§ āĻāĻŦāĻ āĻāĻžāĻ āĻļā§āώ⧠āĻāĻŦāĻžāϰ āĻāĻā§āϰ āĻāĻžā§āĻāĻžā§ āĻĢāĻŋāϰ⧠āĻāϏāĻž āĻšā§āĨ¤
đ Quick Sneak Peak: How Data MovesÂļ
Here is a look at the values before and after a typical instruction execution based on image_4a6205.jpg.
| Component | Initial Value (Start) | Provided Value (Context Based) |
|---|---|---|
| Control Unit | Waiting / Idle | Interpreting Opcode |
| Instruction Flow | Sequential (1, 2, 3...) | Branching to Address B |
| ALU | No active operation | Performing Desired Operation |
| Destination | Undefined | Specified Destination Address |
đēī¸ Visualizing the System OrganizationÂļ
This flowchart visualizes the "Organization of a Stored-program Computer System" shown in Figure 1.2 of your image image_4a6205.jpg.
graph TD
subgraph CPU
A[Control Unit] --- B[ALU]
B --- C[Registers]
end
subgraph Memory
D[Primary Memory] --- E[Secondary Memory]
end
subgraph Input_Output
F[Input Interface] --- G[Input Device/Terminal]
H[Output Interface] --- I[Output Device/Printer]
end
Bus[=== THE SYSTEM BUS ===]
CPU --- Bus
Memory --- Bus
Input_Output --- Bus
â ī¸ Important Warnings for BeginnersÂļ
- â ī¸ Sequential Warning: āϏāĻžāϧāĻžāϰāĻŖāϤ āĻāĻŽā§āĻĒāĻŋāĻāĻāĻžāϰ āϏāĻŋāϰāĻŋā§āĻžāϞāĻŋ āĻāĻžāĻ āĻāϰāϞā§āĻ Branching āĻŦāĻž Subroutine āĻāϰ āϏāĻŽā§ āĻāĻāĻŋ āϞāĻžāĻĢ āĻĻāĻŋā§ā§ āĻ āύā§āϝ āĻāĻžā§āĻāĻžā§ āĻāϞ⧠āϝā§āϤ⧠āĻĒāĻžāϰā§āĨ¤
- â Memory Confusion: āĻŽāύ⧠āϰāĻžāĻāĻŦā§āύ, āĻāύāϏā§āĻā§āϰāĻžāĻāĻļāύ āĻāĻŦāĻ āĻĄā§āĻāĻž āĻāĻā§āĻ āĻāĻŋāύā§āϤ⧠āĻāĻāĻ āĻŽā§āĻŽā§āϰāĻŋāϤ⧠āĻĨāĻžāĻā§, āϝ⧠āĻāĻžāϰāĻŖā§ āĻāĻā§ "Stored-program" āĻāĻŽā§āĻĒāĻŋāĻāĻāĻžāϰ āĻŦāϞā§āĨ¤
- â ī¸ The Role of Bus: āĻāĻĒāύāĻžāϰ āĻāĻŦāĻŋāϰ Figure 1.2 āĻ āϝ⧠'Bus' āĻĻā§āĻāĻž āϝāĻžāĻā§āĻā§, āϏā§āĻāĻŋ āĻŽā§āϞāϤ āĻāĻāĻāĻŋ āĻšāĻžāĻāĻā§ā§ āϝāĻž CPU, Memory āĻāĻŦāĻ I/O āĻĄāĻŋāĻāĻžāĻāϏā§āϰ āĻŽāϧā§āϝ⧠āĻĄā§āĻāĻž āĻāĻĻāĻžāύ-āĻĒā§āϰāĻĻāĻžāύ āĻāϰā§āĨ¤
ā§§. āĻĄā§āĻĄāĻŋāĻā§āĻā§āĻĄ āϰā§āĻāĻŋāϏā§āĻāĻžāϰāϏāĻŽā§āĻš (Dedicated Registers)Âļ
CPU-āĻāϰ āĻāύā§āĻā§āϰā§āϞ āĻāĻāύāĻŋāĻ āϤāĻžāϰ āĻāĻžāĻāĻā§āϞ⧠āϏāĻŽā§āĻĒāύā§āύ āĻāϰāĻžāϰ āĻāύā§āϝ āϤāĻŋāύāĻāĻŋ āĻĒā§āϰāϧāĻžāύ āϰā§āĻāĻŋāϏā§āĻāĻžāϰ āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻāϰā§:
* Program Counter (PC): āĻāĻāĻŋ āĻĒāϰāĻŦāϰā§āϤ⧠āϝ⧠āĻāύāϏā§āĻā§āϰāĻžāĻāĻļāύāĻāĻŋ āĻāĻžāϞāĻžāύ⧠āĻšāĻŦā§, āϤāĻžāϰ āĻŽā§āĻŽā§āϰāĻŋ āĻ
ā§āϝāĻžāĻĄā§āϰā§āϏ āϧāϰ⧠āϰāĻžāĻā§āĨ¤
* Instruction Register (IR): āĻŦāϰā§āϤāĻŽāĻžāύ⧠āϝ⧠āĻāύāϏā§āĻā§āϰāĻžāĻāĻļāύāĻāĻŋ āĻĒā§āϰāϏā§āϏ āĻāϰāĻž āĻšāĻā§āĻā§, āϏā§āĻāĻŋ āĻāĻāĻžāύ⧠āĻĨāĻžāĻā§āĨ¤
* Effective Address Register (EAR): āĻŽā§āĻŽā§āϰāĻŋ āĻĨā§āĻā§ āϝ⧠āĻĄā§āĻāĻž āĻŦāĻž āϤāĻĨā§āϝ āĻāύāϤ⧠āĻšāĻŦā§, āϤāĻžāϰ āϏāĻ āĻŋāĻ āĻ āĻŋāĻāĻžāύāĻž āĻāĻāĻŋ āĻŽāύ⧠āϰāĻžāĻā§āĨ¤
â ī¸ āϏāϤāϰā§āĻāϤāĻž: āĻāĻ āϰā§āĻāĻŋāϏā§āĻāĻžāϰāĻā§āϞ⧠āĻā§āĻŦāϞ āĻāύā§āĻā§āϰā§āϞ āĻāĻāύāĻŋāĻā§āϰ āĻāύā§āϝ āϏāĻāϰāĻā§āώāĻŋāϤāĨ¤ āĻāĻāĻāύ āĻāĻāĻāĻžāϰ āĻŦāĻž āϏāĻžāϧāĻžāϰāĻŖ āĻĒā§āϰā§āĻā§āϰāĻžāĻŽāĻžāϰ āϏāϰāĻžāϏāϰāĻŋ āĻāĻā§āϞ⧠āĻāĻā§āϏā§āϏ āĻāϰāϤ⧠āĻĒāĻžāϰ⧠āύāĻžāĨ¤
⧍. āĻāύā§āĻā§āϰā§āϞ āĻĢā§āϞ⧠(Control Flow Sequences)Âļ
āĻāĻŽā§āĻĒāĻŋāĻāĻāĻžāϰ āϏāĻžāϧāĻžāϰāĻŖāϤ āĻŽā§āĻŽā§āϰāĻŋ āĻĨā§āĻā§ āϏāĻŋāϰāĻŋā§āĻžāϞāĻŋ āĻāĻžāĻ āĻāϰā§, āĻāĻŋāύā§āϤ⧠image_496a64.jpg āĻāϰ Figure 1.3 āĻ āĻĻā§āĻāĻŋ āĻŦā§āϝāϤāĻŋāĻā§āϰāĻŽ āĻĻā§āĻāĻžāύ⧠āĻšā§ā§āĻā§:
* Branch Instruction (Figure 1.3a): āϝāĻāύ āĻŽā§āĻŽā§āϰāĻŋ āϞā§āĻā§āĻļāύ ā§Ē āĻĨā§āĻā§ āϏāϰāĻžāϏāϰāĻŋ āϞā§āĻā§āĻļāύ B-āϤ⧠āϞāĻžāĻĢ āĻĻā§āĻā§āĻž āĻšā§āĨ¤
* Subroutine Call (Figure 1.3b): āϝāĻāύ āĻŽā§āϞ āĻĒā§āϰā§āĻā§āϰāĻžāĻŽ āĻĨāĻžāĻŽāĻŋā§ā§ āĻ
āύā§āϝ āĻāĻāĻāĻŋ āĻā§āĻ āĻĒā§āϰā§āĻā§āϰāĻžāĻŽ (Subprogram) āĻāĻžāϞāĻžāύ⧠āĻšā§ āĻāĻŦāĻ āĻāĻžāĻ āĻļā§āώ⧠'Return' āĻāύāϏā§āĻā§āϰāĻžāĻāĻļāύā§āϰ āĻŽāĻžāϧā§āϝāĻŽā§ āĻāĻŦāĻžāϰ āĻāĻā§āϰ āĻāĻžā§āĻāĻžā§ āĻĢāĻŋāϰ⧠āĻāϏāĻž āĻšā§āĨ¤
đ§ āĻŽā§āĻŽā§āϰāĻŋ āĻāĻāύāĻŋāĻ (Memory Unit Overview)Âļ
āĻāĻŽā§āĻĒāĻŋāĻāĻāĻžāϰā§āϰ āϏāĻŦ āĻĒā§āϰā§āĻā§āϰāĻžāĻŽ āĻāĻŦāĻ āĻĄā§āĻāĻž āĻŽā§āĻŽā§āϰāĻŋāϤ⧠āĻāĻŽāĻž āĻĨāĻžāĻā§āĨ¤ āĻāĻ āĻŽā§āĻŽā§āϰāĻŋāĻā§ āĻŽā§āϞāϤ āĻĻā§āĻāĻŋ āĻāĻžāĻā§ āĻāĻžāĻ āĻāϰāĻž āϝāĻžā§:
- Primary Memory: āĻāĻāĻŋ āϏāϞāĻŋāĻĄ-āϏā§āĻā§āĻ āĻĒā§āϰāϝā§āĻā§āϤāĻŋāϤ⧠āϤā§āϰāĻŋ āĻāĻŦāĻ āĻāĻā§ 'Executable Memory' āĻŦāϞāĻž āĻšā§ āĻāĻžāϰāĻŖ CPU āϏāϰāĻžāϏāϰāĻŋ āĻāĻāĻžāύ āĻĨā§āĻā§ āĻāĻžāĻ āĻāϰāϤ⧠āĻĒāĻžāϰā§āĨ¤
- Secondary Memory: āĻāĻāĻŋ āĻŽā§āϞāϤ āĻŽā§āϝāĻžāĻāύā§āĻāĻŋāĻ āĻĄāĻŋāϏā§āĻ āĻŦāĻž āĻā§āĻĒ āĻāĻžāϤā§ā§ āĻāϞā§āĻāĻā§āϰā§āĻŽā§āĻāĻžāύāĻŋāĻā§āϝāĻžāϞ āĻĄāĻŋāĻāĻžāĻāϏāĨ¤
đ Quick Sneak Peak: Primary vs SecondaryÂļ
| Feature | Primary Memory | Secondary Memory |
|---|---|---|
| Technology | Solid-state | Electromechanical (Disks/Tapes) |
| Speed | Very Fast (Matches CPU) | Slow |
| Cost | High | Low |
| CPU Access | Directly executable | Indirect (Needs swapping) |
đž āĻĒā§āϰāĻžāĻāĻŽāĻžāϰāĻŋ āĻŽā§āĻŽā§āϰāĻŋ: RWM āĻŦāύāĻžāĻŽ ROMÂļ
āĻĒā§āϰāĻžāĻāĻŽāĻžāϰāĻŋ āĻŽā§āĻŽā§āϰāĻŋ āĻāĻŦāĻžāϰ āĻĻā§āĻ āϧāϰāĻŖā§āϰ āĻšā§:
- Read-Write Memory (RWM): āĻāĻāĻžāύ⧠āĻāĻĒāύāĻŋ āĻĄā§āĻāĻž āĻĒā§āϤā§āĻ āĻĒāĻžāϰāĻŦā§āύ āĻāĻŦāĻ āύāϤā§āύ āĻāĻŋāĻā§ āϞāĻŋāĻāϤā§āĻ āĻĒāĻžāϰāĻŦā§āύāĨ¤
- Read-Only Memory (ROM): āĻāĻāĻžāύ āĻĨā§āĻā§ āĻļā§āϧ⧠āĻĄā§āĻāĻž āĻĒā§āĻž āϝāĻžā§āĨ¤ āĻā§āύ āĻāĻŽāϰāĻž ROM āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻāϰāĻŋ?
- đ° Low Price: āĻŦāϰā§āϤāĻŽāĻžāύ⧠āϏāϏā§āϤāĻžā§ ROM āϤā§āϰāĻŋ āĻāϰāĻž āϝāĻžā§āĨ¤
- đ Permanent Info: āĻāĻŋāĻā§ āϤāĻĨā§āϝ āϝā§āĻŽāύ āĻŽāύāĻŋāĻāϰ āĻĒā§āϰā§āĻā§āϰāĻžāĻŽ āĻŦāĻž āĻŽā§āϝāĻžāĻĨāĻŽā§āĻāĻŋāĻā§āϝāĻžāϞ āĻā§āĻŦāĻŋāϞ āĻāĻāύā§āĻ āĻŦāĻĻāϞāĻžāύā§āϰ āĻĒā§āϰā§ā§āĻāύ āĻšā§ āύāĻžāĨ¤
â ī¸ Warning: RWM āĻāĻŦāĻ ROM āĻāĻā§āĻā§āĻ 'Random-Access' āĻĄāĻŋāĻāĻžāĻāϏ āĻŦāϞāĻž āĻšā§ āĻāĻžāϰāĻŖ āĻŽā§āĻŽā§āϰāĻŋāϰ āϝā§āĻā§āύ⧠āĻāĻžā§āĻāĻž āĻĨā§āĻā§ āĻĄā§āĻāĻž āĻāύāϤ⧠āĻāĻāĻ āϏāĻŽā§ āϞāĻžāĻā§āĨ¤
āĻāϏāϞ⧠āĻāĻĒāύāĻŋ āĻāϤāĻā§āώāĻŖ āϝ⧠Read-Write Memory (RWM) āϏāĻŽā§āĻĒāϰā§āĻā§ āĻāĻžāύāĻāĻŋāϞā§āύ, āϏā§āĻāĻŋāĻ āĻšāϞ⧠RAM (Random Access Memory)āĨ¤
āϏāĻšāĻ āĻāĻĨāĻžā§, RAM āĻšāϞ⧠āĻāĻŽā§āĻĒāĻŋāĻāĻāĻžāϰā§āϰ "āĻāĻā§āĻāĻŋāĻ āĻāĻžāĻā§āϰ āĻā§āĻŦāĻŋāϞ"āĨ¤ āĻāĻĒāύāĻžāϰ āĻŦāĻā§ā§āϰ āĻĒāĻžāϤāĻž (image_4904cb.jpg) āĻ āύā§āϝāĻžā§ā§, āĻāĻāĻŋ āĻāĻŽāύ āĻāĻ āϧāϰāĻŖā§āϰ āĻĒā§āϰāĻžāĻāĻŽāĻžāϰāĻŋ āĻŽā§āĻŽā§āϰāĻŋ āϝā§āĻāĻžāύ⧠āϤāĻĨā§āϝ āĻĒā§āĻž āĻāĻŦāĻ āϞā§āĻāĻžâāĻāĻā§āĻ āĻāϰāĻž āϝāĻžā§āĨ¤
āĻā§āύ āĻāĻā§ RAM āĻŦāϞā§? āĻāĻžāϰāĻŖ āĻŽā§āĻŽā§āϰāĻŋāϰ āϝā§āĻā§āύ⧠āĻāĻžā§āĻāĻž (Address) āĻĨā§āĻā§ āϤāĻĨā§āϝ āϏāĻāĻā§āϰāĻš āĻāϰāϤ⧠āĻāĻāĻĻāĻŽ āϏāĻŽāĻžāύ āϏāĻŽā§ āϞāĻžāĻā§, āϝāĻžāĻā§ āĻŦāĻā§ā§ 'Random-access' āĻŦāϞāĻž āĻšā§ā§āĻā§āĨ¤
āĻā§āϞā§āĻāĻžāĻāϞ āĻŽā§āĻŽā§āϰāĻŋ: RAM-āĻāϰ āϏāĻŦāĻā§ā§ā§ āĻŦā§ āĻŦā§āĻļāĻŋāώā§āĻā§āϝ āĻšāϞ⧠āĻāĻāĻŋ āĻ āϏā§āĻĨāĻžā§ā§āĨ¤ āĻŦāĻŋāĻĻā§āϝā§ā§ āĻāϞ⧠āĻā§āϞ⧠āĻāϰ āϏāĻŦ āϤāĻĨā§āϝ āĻŽā§āĻā§ āϝāĻžā§āĨ¤ āϤāĻžāĻ āĻāĻā§ āϏāĻāϰāĻā§āώāĻŋāϤ āĻŦāĻž āϏā§āĻĨāĻžā§ā§ āϤāĻĨā§āϝā§āϰ āĻāύā§āϝ āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻāϰāĻž āĻšā§ āύāĻžāĨ¤
āĻāĻžāĻā§āϰ āϧāϰāĻŖ: āĻāĻĒāύāĻŋ āϝāĻāύ āĻā§āύ⧠āĻ ā§āϝāĻžāĻĒ āĻŦāĻž āĻā§āĻŽ āĻāĻĒā§āύ āĻāϰā§āύ, āϏā§āĻāĻŋ āϏā§āĻā§āύā§āĻĄāĻžāϰāĻŋ āĻŽā§āĻŽā§āϰāĻŋ (āϝā§āĻŽāύ: SSD āĻŦāĻž Hard Disk) āĻĨā§āĻā§ āϞāĻžāĻĢ āĻĻāĻŋā§ā§ RAM-āĻ āĻāϞ⧠āĻāϏ⧠āϝāĻžāϤ⧠CPU āĻĻā§āϰā§āϤ āϏā§āĻāĻŋ āĻāĻā§āϏā§āϏ āĻāϰāϤ⧠āĻĒāĻžāϰā§āĨ¤
āĻāĻĒāύāĻžāϰ āĻļā§ā§āĻžāϰ āĻāϰāĻž image_4c7d03.jpg āĻĢāĻžāĻāϞāĻāĻŋāϤ⧠āĻāĻŽā§āĻĒāĻŋāĻāĻāĻžāϰā§āϰ āϝā§āĻāĻžāϝā§āĻā§āϰ āϰāĻžāϏā§āϤāĻž āĻ āϰā§āĻĨāĻžā§ System Bus āĻāĻŦāĻ āĻāĻŽā§āĻĒāĻŋāĻāĻāĻžāϰā§āϰ āĻāĻ āύ āĻŦāĻž Structures āύāĻŋā§ā§ āĻāϞā§āĻāύāĻž āĻāϰāĻž āĻšā§ā§āĻā§āĨ¤ āĻāϞā§āύ āĻāĻāĻĻāĻŽ āĻā§ā§āĻž āĻĨā§āĻā§ āĻāĻāĻŋ āĻŦā§āĻā§ āύā§āĻā§āĻž āϝāĻžāĻāĨ¤Âļ
ā§§. āϏāĻŋāϏā§āĻā§āĻŽ āĻŦāĻžāϏ (The System Bus) đÂļ
āĻāĻŽā§āĻĒāĻŋāĻāĻāĻžāϰā§āϰ āĻŦāĻŋāĻāĻŋāύā§āύ āĻ
āĻāĻļ āϝ⧠āϤāĻžāϰā§āϰ āĻŽāĻžāϧā§āϝāĻŽā§ āĻāĻā§ āĻ
āĻĒāϰā§āϰ āϏāĻžāĻĨā§ āĻāĻĨāĻž āĻŦāϞā§, āϤāĻžāĻā§āĻ Bus āĻŦāϞā§āĨ¤ āĻāĻāĻŋ āϤāĻŋāύ āĻĒā§āϰāĻāĻžāϰ:
* Address Bus: āĻāĻāĻŋ āĻā§āĻŦāϞ āĻāĻāĻŽā§āĻā§ (Unidirectional)āĨ¤ āĻĒā§āϰāϏā§āϏāϰ āĻā§āύ āĻŽā§āĻŽā§āϰāĻŋ āĻŦāĻž āĻĄāĻŋāĻāĻžāĻāϏā§āϰ āϏāĻžāĻĨā§ āĻāĻžāĻ āĻāϰāĻŦā§, āϤāĻžāϰ āĻ āĻŋāĻāĻžāύāĻž āĻŦāĻž āĻ
ā§āϝāĻžāĻĄā§āϰā§āϏ āĻāĻāĻŋ āĻĻāĻŋā§ā§ āĻĒāĻžāĻ āĻžā§āĨ¤ ā§Šā§¨-āĻŦāĻŋāĻā§āϰ āĻŦāĻžāϏ āĻšāϞ⧠āĻāĻāĻŋ ā§Ē āĻŦāĻŋāϞāĻŋā§āύā§āϰ āĻŦā§āĻļāĻŋ āĻāĻžā§āĻāĻž āĻā§āĻāĻā§ āĻĒā§āϤ⧠āĻĒāĻžāϰā§āĨ¤
* Data Bus: āĻāĻāĻŋ āĻāĻāĻŽā§āĻā§ (Bidirectional)āĨ¤ āĻĒā§āϰāϏā§āϏāϰ āĻāĻŦāĻ āĻŽā§āĻŽā§āϰāĻŋāϰ āĻŽāϧā§āϝ⧠āϤāĻĨā§āϝ āĻāĻĻāĻžāύ-āĻĒā§āϰāĻĻāĻžāύ āĻāϰāĻžāϰ āϰāĻžāϏā§āϤāĻž āĻāĻāĻŋāĨ¤
* Control Bus: āĻāĻāĻŋ āĻā§āϰāĻžāĻĢāĻŋāĻ āĻĒā§āϞāĻŋāĻļā§āϰ āĻŽāϤā§āĨ¤ āĻāĻāĻŋ āύāĻŋāϰā§āĻĻā§āĻļ āĻĻā§ā§ āϝ⧠āĻāĻāύ āĻĄā§āĻāĻž āĻĒā§āĻž āĻšāĻŦā§ āύāĻžāĻāĻŋ āϞā§āĻāĻž āĻšāĻŦā§ āĻāĻŦāĻ āϏāĻŦ āĻĄāĻŋāĻāĻžāĻāϏāĻā§ āϏāĻŋāύāĻā§āϰā§āύāĻžāĻāĻ āĻāϰā§āĨ¤
⧍. āĻāĻŽā§āĻĒāĻŋāĻāĻāĻžāϰ āϏā§āĻā§āϰāĻžāĻāĻāĻžāϰ (Computer Structures) đī¸Âļ
āĻāĻŽā§āĻĒāĻŋāĻāĻāĻžāϰāĻā§āϞ⧠āĻā§āĻāĻžāĻŦā§ āĻĄā§āĻāĻž āĻĒā§āϰāϏā§āϏ āĻāϰā§, āϤāĻžāϰ āĻāĻĒāϰ āĻāĻŋāϤā§āϤāĻŋ āĻāϰ⧠āĻāĻĻā§āϰ āϤāĻŋāύ āĻāĻžāĻā§ āĻāĻžāĻ āĻāϰāĻž āĻšā§ā§āĻā§:
* General Register Machines: āĻāĻāĻžāύ⧠āĻ
āύā§āĻāĻā§āϞ⧠āĻĒāĻā§āĻ āĻŦāĻž āϰā§āĻāĻŋāϏā§āĻāĻžāϰ (\(R_0\) āĻĨā§āĻā§ \(R_7\)) āĻĨāĻžāĻā§ āĻĄā§āĻāĻž āϰāĻžāĻāĻžāϰ āĻāύā§āϝāĨ¤
* Accumulator Based Machines: āĻāĻāĻžāύ⧠āĻāĻāĻāĻŋ āĻĒā§āϰāϧāĻžāύ āϰā§āĻāĻŋāϏā§āĻāĻžāϰ āĻĨāĻžāĻā§ āϝāĻž āĻĻāĻŋā§ā§ āϏāĻŦ āĻāĻžāĻ āĻšā§āĨ¤
* Stack Machines: āĻāĻāĻŋ āĻāĻāĻāĻŋ āĻĨāĻžāϞāĻžāϰ āϏā§āϤā§āĻĒā§āϰ āĻŽāϤ⧠āĻāĻžāĻ āĻāϰā§āĨ¤
â ī¸ āĻŽāύ⧠āϰāĻžāĻāĻŦā§āύ: Flag Register (F) āĻā§āĻŦ āĻā§āϰā§āϤā§āĻŦāĻĒā§āϰā§āĻŖāĨ¤ āĻāĻāĻŋ āĻŦāϞ⧠āĻĻā§ā§ āĻā§āύ⧠āϝā§āĻāĻĢāϞ āĻāĻŋ āĻļā§āύā§āϝ āĻšā§ā§āĻā§ (Z-flag) āύāĻžāĻāĻŋ āĻšāĻžāϤ⧠āĻāĻŋāĻā§ āϰā§ā§ āĻā§āĻā§ (Carry flag)āĨ¤
āĻāĻĒāύāĻžāϰ āĻĻā§āĻā§āĻž āĻāĻŦāĻŋāĻāĻŋ āĻāĻāĻāĻŋ āϏāĻžāϧāĻžāϰāĻŖ āϰā§āĻāĻŋāϏā§āĻāĻžāϰ āĻĒā§āϰāϏā§āϏāϰā§āϰ (General Register Processor) āĻāĻ āύ āĻŦāĻž āĻāϰā§āĻāĻŋāĻā§āĻāĻāĻžāϰ āϤā§āϞ⧠āϧāϰāĻā§āĨ¤ āύāĻŋāĻā§ āĻĄāĻžā§āĻžāĻā§āϰāĻžāĻŽā§āϰ āĻĒā§āϰāϤāĻŋāĻāĻŋ āĻ āĻāĻļā§āϰ āĻŦāĻŋāϏā§āϤāĻžāϰāĻŋāϤ āĻŦā§āϝāĻžāĻā§āϝāĻž āĻŦāĻžāĻāϞāĻžā§ āĻĻā§āĻā§āĻž āĻšāϞā§:
āĻāĻŋāϤā§āϰ ā§§.ā§Ē: āĻāĻāĻāĻŋ āϏāĻžāϧāĻžāϰāĻŖ āϰā§āĻāĻŋāϏā§āĻāĻžāϰ āĻĒā§āϰāϏā§āϏāϰā§āϰ āĻāĻ āύ (Organization of a Typical General Register Processor)Âļ
āĻāĻ āĻĄāĻžā§āĻžāĻā§āϰāĻžāĻŽāĻāĻŋ āĻŽā§āϞāϤ āĻĒā§āϰāϏā§āϏāϰā§āϰ āĻā§āϤāϰā§āϰ āĻŦāĻŋāĻāĻŋāύā§āύ āĻ āĻāĻļ āĻāĻŦāĻ āϤāĻžāϰāĻž āĻā§āĻāĻžāĻŦā§ āĻāĻā§ āĻ āĻĒāϰā§āϰ āϏāĻžāĻĨā§ āϝā§āĻā§āϤ āĻĨāĻžāĻā§ āϤāĻž āĻĻā§āĻāĻžā§āĨ¤
ā§§. āĻā§āύāĻžāϰā§āϞ āϰā§āĻāĻŋāϏā§āĻāĻžāϰ (General Registers: R0 - R7)Âļ
- āĻāĻāĻžāύ⧠āĻŽā§āĻ ā§ŽāĻāĻŋ āϏāĻžāϧāĻžāϰāĻŖ āϰā§āĻāĻŋāϏā§āĻāĻžāϰ āϰā§ā§āĻā§ (R0 āĻĨā§āĻā§ R7)āĨ¤
- āĻāĻžāĻ: āĻāĻā§āϞ⧠āĻĄā§āĻāĻž, āĻŽā§āĻŽā§āϰāĻŋ āĻ ā§āϝāĻžāĻĄā§āϰā§āϏ āĻ āĻĨāĻŦāĻž āĻā§āύ⧠āĻāĻžāĻŖāĻŋāϤāĻŋāĻ āĻŦāĻž āϞāĻāĻŋāĻā§āϝāĻžāϞ āĻ āĻĒāĻžāϰā§āĻļāύā§āϰ āĻĢāϞāĻžāĻĢāϞ āϏāĻžāĻŽā§āĻŋāĻāĻāĻžāĻŦā§ āĻāĻŽāĻž āϰāĻžāĻāĻžāϰ āĻāύā§āϝ āĻŦā§āϝāĻŦāĻšā§āϤ āĻšā§āĨ¤
⧍. PC (Program Counter)Âļ
- āĻāĻžāĻ: āĻĒā§āϰāϏā§āϏāϰ āĻŦāϰā§āϤāĻŽāĻžāύ⧠āϝ⧠āύāĻŋāϰā§āĻĻā§āĻļāĻāĻŋ (Instruction) āĻĒāĻžāϞāύ āĻāϰāĻā§, āϤāĻžāϰ āĻ āĻŋāĻ āĻĒāϰā§āϰ āύāĻŋāϰā§āĻĻā§āĻļā§āϰ āĻŽā§āĻŽā§āϰāĻŋ āĻ ā§āϝāĻžāĻĄā§āϰā§āϏ āĻŦāĻž āĻ āĻŋāĻāĻžāύāĻž āĻāĻ āϰā§āĻāĻŋāϏā§āĻāĻžāϰ⧠āĻāĻŽāĻž āĻĨāĻžāĻā§āĨ¤ āĻāĻāĻŋ āĻāĻŽā§āĻĒāĻŋāĻāĻāĻžāϰāĻā§ āĻĒāϰāĻŦāϰā§āϤ⧠āĻāĻžāĻā§āϰ āĻĻāĻŋāĻāύāĻŋāϰā§āĻĻā§āĻļāύāĻž āĻĻā§ā§āĨ¤
ā§Š. EAR (Effective Address Register)Âļ
- āĻāĻžāĻ: āĻŽā§āĻŽā§āϰāĻŋ āĻĨā§āĻā§ āϝāĻāύ āĻā§āύ⧠āĻĄā§āĻāĻž āύāĻŋāϤ⧠āĻŦāĻž āĻĒāĻžāĻ āĻžāϤ⧠āĻšā§, āϤāĻāύ āϏā§āĻ āύāĻŋāϰā§āĻĻāĻŋāώā§āĻ āĻŽā§āĻŽā§āϰāĻŋ āϞā§āĻā§āĻļāύā§āϰ āĻ ā§āϝāĻžāĻĄā§āϰā§āϏ āĻāĻ āϰā§āĻāĻŋāϏā§āĻāĻžāϰ⧠āϏāĻāϰāĻā§āώāĻŋāϤ āĻĨāĻžāĻā§āĨ¤
ā§Ē. SP (Stack Pointer)Âļ
- āĻāĻāĻŋ āĻāĻāĻāĻŋ āĻŦāĻŋāĻļā§āώ āĻŦāĻž āĻĄā§āĻĄāĻŋāĻā§āĻā§āĻĄ āϰā§āĻāĻŋāϏā§āĻāĻžāϰāĨ¤
- āĻāĻžāĻ: āĻāĻāĻŋ āĻŽā§āĻŽā§āϰāĻŋāϰ āĻāĻāĻāĻŋ āĻŦāĻŋāĻļā§āώ āĻ āĻāĻļ 'āϏā§āĻā§āϝāĻžāĻ'-āĻāϰ āĻāĻāĻĻāĻŽ āĻāĻĒāϰā§āϰ āĻāϞāĻŋāĻŽā§āύā§āĻā§āϰ āĻ āĻŋāĻāĻžāύāĻž āĻŦāĻž āĻ ā§āϝāĻžāĻĄā§āϰā§āϏ āϧāϰ⧠āϰāĻžāĻā§āĨ¤
ā§Ģ. IR (Instruction Register) āĻ āĻāύā§āĻā§āϰā§āϞ āĻāĻāύāĻŋāĻ (Control Unit)Âļ
- IR: āĻĒā§āϰāϏā§āϏāϰ āĻŦāϰā§āϤāĻŽāĻžāύ⧠āϝ⧠āύāĻŋāϰā§āĻĻā§āĻļāĻāĻŋ āύāĻŋā§ā§ āĻāĻžāĻ āĻāϰāĻā§, āϏā§āĻāĻŋ āĻāĻāĻžāύ⧠āĻĨāĻžāĻā§āĨ¤
- āĻāύā§āĻā§āϰā§āϞ āĻāĻāύāĻŋāĻ: āĻāĻāĻŋ āĻĒā§āϰāϏā§āϏāϰā§āϰ 'āĻŽāϏā§āϤāĻŋāώā§āĻ' āĻšāĻŋāϏā§āĻŦā§ āĻāĻžāĻ āĻāϰā§āĨ¤ āĻāĻāĻŋ IR āĻĨā§āĻā§ āύāĻŋāϰā§āĻĻā§āĻļ āĻĒā§ā§ āĻāĻŦāĻ āϏā§āĻ āĻ āύā§āϝāĻžā§ā§ ALU āĻ āĻ āύā§āϝāĻžāύā§āϝ āĻ āĻāĻļāĻā§ āĻāĻžāĻ āĻāϰāĻžāϰ āϏāĻŋāĻāύā§āϝāĻžāϞ āĻĻā§ā§āĨ¤
ā§Ŧ. ALU (Arithmetic Logic Unit)Âļ
- āĻāĻžāĻ: āĻāĻŽā§āĻĒāĻŋāĻāĻāĻžāϰā§āϰ āϝāĻžāĻŦāϤā§ā§ āĻāĻžāĻŖāĻŋāϤāĻŋāĻ āĻāĻžāĻ (āϝā§āĻŽāύ: āϝā§āĻ, āĻŦāĻŋā§ā§āĻ, āĻā§āĻŖ, āĻāĻžāĻ) āĻāĻŦāĻ āϝā§āĻā§āϤāĻŋāĻ āĻŦāĻž āϞāĻāĻŋāĻā§āϝāĻžāϞ āĻāĻžāĻ āĻāĻ āĻ āĻāĻļā§ āϏāĻŽā§āĻĒāύā§āύ āĻšā§āĨ¤ āĻĄāĻžā§āĻžāĻā§āϰāĻžāĻŽā§ āĻĻā§āĻāĻž āϝāĻžāĻā§āĻā§, āĻā§āύāĻžāϰā§āϞ āϰā§āĻāĻŋāϏā§āĻāĻžāϰ āĻĨā§āĻā§ āĻĄā§āĻāĻž āϏāϰāĻžāϏāϰāĻŋ ALU-āϤ⧠āĻĒā§āϰāĻŦāĻžāĻšāĻŋāϤ āĻšāĻā§āĻā§āĨ¤
ā§. F (Flag Register)Âļ
- āĻāĻā§ āϏā§āĻā§āϝāĻžāĻāĻžāϏ āϰā§āĻāĻŋāϏā§āĻāĻžāϰ āĻŦāĻž āĻĢā§āϞā§āϝāĻžāĻ āϰā§āĻāĻŋāϏā§āĻāĻžāϰ āĻŦāϞāĻž āĻšā§āĨ¤
- āĻāĻžāĻ: āĻāĻāĻŋ ALU-āϤ⧠āĻāϰāĻž āĻā§āύ⧠āĻ āĻĒāĻžāϰā§āĻļāύā§āϰ āĻĢāϞāĻžāĻĢāϞ āĻŦāĻž āĻ āĻŦāϏā§āĻĨāĻžāϰ āϤāĻĨā§āϝ āĻĻā§ā§āĨ¤ āϝā§āĻŽāύ: āϝāĻĻāĻŋ āĻā§āύ⧠āĻšāĻŋāϏāĻžāĻŦā§āϰ āĻĢāϞāĻžāĻĢāϞ āĻļā§āύā§āϝ (Zero) āĻšā§, āϤāĻŦā§ āĻāϰ Z-flag ā§§ āĻšā§ā§ āϝāĻžā§āĨ¤ āĻāϤ⧠āĻā§āϝāĻžāϰāĻŋ āĻĢā§āϞā§āϝāĻžāĻ (Carry flag)-āĻ āĻĨāĻžāĻā§āĨ¤
ā§Ž. Memory and I/O InterfaceÂļ
- āĻāĻžāĻ: āĻāĻ āĻ āĻāĻļā§āϰ āĻŽāĻžāϧā§āϝāĻŽā§ āĻĒā§āϰāϏā§āϏāϰ āĻāĻŽā§āĻĒāĻŋāĻāĻāĻžāϰā§āϰ āĻŽā§āϞ āĻŽā§āĻŽā§āϰāĻŋ (RAM) āĻāĻŦāĻ āĻŦāĻŋāĻāĻŋāύā§āύ āĻāύāĻĒā§āĻ/āĻāĻāĻāĻĒā§āĻ āĻĄāĻŋāĻāĻžāĻāϏā§āϰ (āϝā§āĻŽāύ- āĻāĻŋāĻŦā§āϰā§āĻĄ, āĻĄāĻŋāϏāĻĒā§āϞā§) āϏāĻžāĻĨā§ āϝā§āĻāĻžāϝā§āĻ āĻāϰā§āĨ¤
⧝. āĻĄā§āĻāĻž āĻ āĻ ā§āϝāĻžāĻĄā§āϰā§āϏ āĻĒāĻžāĻĨ (Arrows/Buses)Âļ
- āĻĄāĻžā§āĻžāĻā§āϰāĻžāĻŽā§āϰ āϤā§āϰ āĻāĻŋāĻšā§āύāĻā§āϞ⧠āĻŽā§āϞāϤ āϤāĻĨā§āϝ āĻāϞāĻžāĻāϞā§āϰ āĻĒāĻĨ āĻŦāĻž 'āĻŦāĻžāϏ' (Bus) āύāĻŋāϰā§āĻĻā§āĻļ āĻāϰā§āĨ¤ āĻāĻ āĻĒāĻĨāĻā§āϞ⧠āĻĻāĻŋā§ā§āĻ āĻĄā§āĻāĻž āĻāĻŦāĻ āĻ ā§āϝāĻžāĻĄā§āϰā§āϏ āĻŦāĻŋāĻāĻŋāύā§āύ āϰā§āĻāĻŋāϏā§āĻāĻžāϰ āĻ āĻŽā§āĻŽā§āϰāĻŋāϰ āĻŽāϧā§āϝ⧠āĻāĻĻāĻžāύ-āĻĒā§āϰāĻĻāĻžāύ āĻāϰāĻž āĻšā§āĨ¤
āϏāĻāĻā§āώā§āĻĒā§ āύāĻŋāϰā§āĻĻā§āĻļā§āϰ āϧāϰāύ (Instruction Types):
āĻāĻ āϧāϰāύā§āϰ āĻĒā§āϰāϏā§āϏāϰ āϏāĻžāϧāĻžāϰāĻŖāϤ āĻĻā§āĻ āϧāϰāύā§āϰ āύāĻŋāϰā§āĻĻā§āĻļ āϏāĻŽāϰā§āĻĨāύ āĻāϰā§:
* Three-address instructions: āϝā§āĻŽāύ ADD x, y, z (āĻāĻāĻžāύ⧠x āĻāĻŦāĻ y āϝā§āĻ āĻāϰ⧠āĻĢāϞāĻžāĻĢāϞ z-āĻ āϰāĻžāĻāĻž āĻšā§)āĨ¤
* Two-address instructions: āϝā§āĻŽāύ MOV x, y (āĻāĻāĻžāύ⧠x-āĻāϰ āĻŽāĻžāύ y-āϤ⧠āĻāĻĒāĻŋ āĻāϰāĻž āĻšā§)āĨ¤
English Version (Easy/Indian Style)Âļ
1. Important Registers to RememberÂļ
The Control Unit uses these registers to finish any task properly:
* Program Counter (PC): This box holds the address of the next instruction which the computer will run.
* Instruction Register (IR): This box holds the instruction which is running right now.
* Effective Address Register (EAR): This box keeps the address of the data we need to get from the memory.
2. How Computer Changes its PathÂļ
Normally, computer goes 1, 2, 3... in order. But in Figure 1.3, it shows two special cases:

* Branching (Jump): Look at picture 'a', the computer is at location 4, but suddenly it jumps to Location B. It skips the middle steps! đ
* Subroutine (Call): In picture 'b', at location 5, it calls a mini-program at location S. After finishing that work, it uses a Return instruction to come back to location 6. đ
đ Quick Summary TableÂļ
| Register Name | What it does? | Can you touch it? |
|---|---|---|
| PC | Holds NEXT address | â No, it's dedicated! |
| IR | Holds CURRENT work | â No, only for Control Unit! |
| EAR | Holds DATA address | â No, it's private! |
â ī¸ Warning Emoji SectionÂļ
- â X Emoji: You cannot access these registers via your normal program because they are "Dedicated".
- â ī¸ Warning: If the Return instruction is missing in a Subroutine, the computer will get lost and won't know how to come back to the main program!
Boss, listen carefully. If we store everything in Solid-state memory, it will be very costly. That is why we use Secondary Memory like magnetic disks. It is a bit slow (turtle speed đĸ), but it can store huge files like your text editors or assemblers very cheaply.
To keep the computer fast, we use Memory-management algorithms. These algorithms "swap" data between primary and secondary memory in small pieces. So the CPU always finds its required item in the fast Primary memory.
đ ī¸ Typical Data Values ExampleÂļ
Based on the text, let's see how values are handled:
| Component | Initial Value (Empty/Default) | Provided Value (In Context) |
|---|---|---|
| RWM Word Size | 0 bits | 8-bit words |
| ROM Content | Empty | Unalterable info (e.g., Op-code table) |
| Secondary Memory | Offline | Huge Data Files/Programs |
â¨ī¸ I/O Devices & InterfaceÂļ
āĻāĻāĻāĻžāϰ āĻāĻžāϰā§āĻŽāĻŋāύāĻžāϞ āĻŦāĻž āĻĒā§āϰāĻŋāύā§āĻāĻžāϰ āĻĻāĻŋā§ā§ āĻāĻŽāϰāĻž āĻāĻŽā§āĻĒāĻŋāĻāĻāĻžāϰā§āϰ āϏāĻžāĻĨā§ āĻāĻĨāĻž āĻŦāϞāĻŋāĨ¤ āĻāĻŋāύā§āϤ⧠āϏāĻŽāϏā§āϝāĻž āĻšāϞ⧠CPU āĻā§āĻŦ āĻĢāĻžāϏā§āĻ āĻāϰ āĻāĻ āĻĄāĻŋāĻāĻžāĻāϏāĻā§āϞ⧠āϏā§āϞā§āĨ¤ āϤāĻžāĻ āĻāĻĻā§āϰ āĻŽāϧā§āϝ⧠āĻāĻžāĻŦ āĻāĻŽāĻžāύā§āϰ āĻāύā§āϝ Interface Circuitry āĻĒā§āϰā§ā§āĻāύ āĻšā§āĨ¤
đēī¸ Visualizing the Memory Evolution & FlowÂļ
Since you asked for timelines, here is a logical flow based on the tech mentioned
graph TD
subgraph "Year 1950s-1970s (Magnetic Era)"
A[Magnetic Tapes/Disks] -->|Used as| B(Secondary Memory)
end
subgraph "Year 1980s-Present (Solid State Era)"
C[IC Technology] -->|Creates| D(ROM & RWM)
D -->|Organized as| E[8-bit Words]
end
B <-.->|Swapping via Algorithms| D
D <--->|Direct Access| F[CPU]
G[I/O Devices: Printer/Terminal] --- H{Interface Circuitry}
H --- F
đĢ Final Check of RulesÂļ
- â X Emoji: ROM-āĻāϰ āĻā§āϤāϰ⧠āĻĨāĻžāĻāĻž 'Monitor Programs' āĻāĻĒāύāĻŋ āϰāĻžāĻāĻ āĻŦāĻž āĻĄāĻŋāϞāĻŋāĻ āĻāϰāϤ⧠āĻĒāĻžāϰāĻŦā§āύ āύāĻžāĨ¤
- â ī¸ Warning: CPU āĻāĻāύā§āĻ āϏāϰāĻžāϏāϰāĻŋ āϏā§āĻā§āύā§āĻĄāĻžāϰāĻŋ āĻŽā§āĻŽā§āϰāĻŋāϰ āϏāĻžāĻĨā§ āĻāĻĨāĻž āĻŦāϞ⧠āύāĻž, āϏāĻŦāϏāĻŽā§ āĻĒā§āϰāĻžāĻāĻŽāĻžāϰāĻŋ āĻŽā§āĻŽā§āϰāĻŋ āĻšā§ā§ āĻāĻžāĻ āĻāϰā§āĨ¤
1. Three Types of Busses (The Highway) đŖī¸Âļ
A Bus is just a set of wires to carry information.
* Address Bus: It is a "One-Way" street. CPU only sends address to Memory or I/O. If you have a 32-bit bus, you can find \(2^{32}\) (4 billion!) locations.
* Data Bus: It is a "Two-Way" street. Information goes from CPU to Memory and comes back also.
* Control Bus: It is like the "Traffic Signal". It tells everyone when to start or stop the I/O work.
2. Specialized Registers (The CPU's Pockets) đī¸Âļ
- General Registers (\(R_0\) to \(R_7\)): Think of these as 8 small temporary pockets to store numbers or logic results.
- Stack Pointer (SP): A special dedicated register that points to the top of the "Stack".
- F Register (Flags): This is the "Status Report" box. If the last math result was zero, it sets the Z-flag to 1.
đ Quick Sneak Peak: Operation Logic ExampleÂļ
Let's look at the ADD x, y, z instruction mentioned in image_4c7d03.jpg. This means: "Take value of x, add it to y, and store the result in z."
| Register/Location | Initial Value (Before ADD) | Provided Value (After ADD x, y, z) |
|---|---|---|
| Location x | 10 |
10 (Stays same) |
| Location y | 20 |
20 (Stays same) |
| Location z | 0 |
30 (New sum) |
| Z-Flag (in F) | 0 |
0 (Since sum is not zero) |
đēī¸ Visualizing the Computer HierarchyÂļ
graph TD
subgraph "System Bus Layer"
A[Address Bus - Unidirectional] --> B[Memory/IO]
C[Data Bus - Bidirectional] <--> B
D[Control Bus - Signals] --> B
end
subgraph "CPU Organization Types"
E[General Register]
F[Accumulator]
G[Stack Machine]
end
B --- E
đĢ Common Pitfalls for BeginnersÂļ
- â Unidirectional vs Bidirectional: Never say Address bus is two-way. It is only one-way from the processor.
- â ī¸ The 32-bit Logic: If the bus size increases, the CPU can handle more memory. That's why modern computers are 64-bit!
- â Flags: Don't forget the F register. It tells the CPU if there was a math error or a zero result.



