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đŸ’ģ āĻ•āĻŽā§āĻĒāĻŋāωāϟāĻžāϰ āφāϏāϞ⧇ āϕ⧀? (The Basics)Âļ

🧠 āĻ•āĻ¨ā§āĻŸā§āϰ⧋āϞ āχāωāύāĻŋāϟ (The Manager)Âļ

āϏāĻŦāĻ•āĻŋāϛ⧁āϰ āĻŽā§‚āϞ āϚāĻžāϞāĻŋāĻ•āĻžāĻļāĻ•ā§āϤāĻŋ āĻšāϞ⧋ Control Unit (CU)āĨ¤ āĻāϟāĻŋ CPU-āĻāϰ āϭ⧇āϤāϰ⧇ āĻĨāĻžāϕ⧇ āĻāĻŦāĻ‚ āĻĒ⧁āϰ⧋ āĻ•āĻžāϜāϟāĻŋāϕ⧇ āĻĻ⧁āϟāĻŋ āĻĒā§āϰāϧāĻžāύ āĻ­āĻžāϗ⧇ āĻ­āĻžāĻ— āĻ•āϰ⧇:

  1. Instruction Interpretation (āĻŦā§āϝāĻžāĻ–ā§āϝāĻžāĻ•āϰāĻŖ): āĻĒā§āϰāĻĨāĻŽā§‡ āĻ•āĻ¨ā§āĻŸā§āϰ⧋āϞ āχāωāύāĻŋāϟ āĻŽā§‡āĻŽā§‹āϰāĻŋ āĻĨ⧇āϕ⧇ āĻāĻ•āϟāĻŋ āχāύāĻ¸ā§āĻŸā§āϰāĻžāĻ•āĻļāύ āĻĒā§œā§‡ āĻāĻŦāĻ‚ āĻŦā§‹āĻāĻžāϰ āĻšā§‡āĻˇā§āϟāĻž āĻ•āϰ⧇ āϝ⧇ āĻāϟāĻŋ āφāϏāϞ⧇ āϕ⧀ āĻ•āϰāϤ⧇ āĻŦāϞāĻž āĻšā§Ÿā§‡āϛ⧇ (āϝ⧇āĻŽāύ: āϝ⧋āĻ— āύāĻžāĻ•āĻŋ āĻŦāĻŋāϝāĻŧā§‹āĻ—)āĨ¤ āĻāϰāĻĒāϰ āϏ⧇ āĻĒā§āĻ°ā§Ÿā§‹āϜāĻ¨ā§€ā§Ÿ āĻĄā§‡āϟāĻž āϏāĻ‚āĻ—ā§āϰāĻš āĻ•āϰ⧇ ALU (Arithmetic Logic Unit)-āϕ⧇ āĻ•āĻžāϜ āĻļ⧁āϰ⧁ āĻ•āϰāĻžāϰ āϏāĻŋāĻ—āĻ¨ā§āϝāĻžāϞ āĻĻā§‡ā§ŸāĨ¤
  2. Instruction Sequencing (āĻ•ā§āϰāĻŽ āύāĻŋāĻ°ā§āϧāĻžāϰāĻŖ): āϏāĻžāϧāĻžāϰāĻŖāϤ āĻ•āĻŽā§āĻĒāĻŋāωāϟāĻžāϰ āĻāĻ•āϟāĻžāϰ āĻĒāϰ āĻāĻ•āϟāĻž āχāύāĻ¸ā§āĻŸā§āϰāĻžāĻ•āĻļāύ āϏāĻŋāϰāĻŋ⧟āĻžāϞāĻŋ āĻĒāĻžāϞāύ āĻ•āϰ⧇āĨ¤ āĻ•āĻ¨ā§āĻŸā§āϰ⧋āϞ āχāωāύāĻŋāϟ āĻ āĻŋāĻ• āĻ•āϰ⧇ āĻĻā§‡ā§Ÿ āĻĒāϰāĻŦāĻ°ā§āϤ⧀ āϕ⧋āύ āĻ•āĻžāϜāϟāĻŋ āĻ•āϰāϤ⧇ āĻšāĻŦ⧇āĨ¤

🔄 āĻŦā§āϝāϤāĻŋāĻ•ā§āϰāĻŽā§€ āĻĒāϰāĻŋāĻ¸ā§āĻĨāĻŋāϤāĻŋ (Exceptions to the Rule)Âļ

āϏāĻŦāϏāĻŽā§Ÿ āϝ⧇ āĻ•āĻŽā§āĻĒāĻŋāωāϟāĻžāϰ āϏ⧋āϜāĻž āĻĒāĻĨ⧇ āϚāϞ⧇ āϤāĻž āύ⧟āĨ¤ āĻŽāĻžāĻā§‡ āĻŽāĻžāĻā§‡ āϤāĻžāϕ⧇ āϞāĻžāχāύ āĻĨ⧇āϕ⧇ āĻŦāĻŋāĻšā§āϝ⧁āϤ āĻšāϤ⧇ āĻšā§ŸāĨ¤ āφāĻĒāύāĻžāϰ āĻ›āĻŦāĻŋāϤ⧇ āĻĻ⧁āϟāĻŋ āĻĒā§āϰāϧāĻžāύ āĻĒāϰāĻŋāĻ¸ā§āĻĨāĻŋāϤāĻŋāϰ āĻ•āĻĨāĻž āĻŦāϞāĻž āĻšā§Ÿā§‡āϛ⧇:

  • Branch Instruction (āĻŦā§āϰāĻžāĻžā§āϚāĻŋāĻ‚): āϝāĻ–āύ āĻ•āĻŽā§āĻĒāĻŋāωāϟāĻžāϰāϕ⧇ āĻŦāϞāĻž āĻšā§Ÿ āϏ⧋āϜāĻž āύāĻž āĻ—āĻŋā§Ÿā§‡ āĻ…āĻ¨ā§āϝ āϕ⧋āύ⧋ āĻ…ā§āϝāĻžāĻĄā§āϰ⧇āϏ⧇ (āϧāϰāĻž āϝāĻžāĻ• Address B) āϞāĻžāĻĢ āĻĻāĻŋā§Ÿā§‡ āϚāϞ⧇ āϝ⧇āϤ⧇āĨ¤
  • Subroutine Calls (āϏāĻžāĻŦāϰ⧁āϟāĻŋāύ): āϝāĻ–āύ āĻŽā§‚āϞ āĻĒā§āϰ⧋āĻ—ā§āϰāĻžāĻŽ āĻĨāĻžāĻŽāĻŋā§Ÿā§‡ āϛ⧋āϟ āĻāĻ•āϟāĻŋ āωāĻĒ-āĻĒā§āϰ⧋āĻ—ā§āϰāĻžāĻŽ (Subprogram) āϚāĻžāϞāĻžāύ⧋ āĻšā§Ÿ āĻāĻŦāĻ‚ āĻ•āĻžāϜ āĻļ⧇āώ⧇ āφāĻŦāĻžāϰ āφāϗ⧇āϰ āϜāĻžā§ŸāĻ—āĻžā§Ÿ āĻĢāĻŋāϰ⧇ āφāϏāĻž āĻšā§ŸāĨ¤

📊 Quick Sneak Peak: How Data MovesÂļ

Here is a look at the values before and after a typical instruction execution based on image_4a6205.jpg.

Component Initial Value (Start) Provided Value (Context Based)
Control Unit Waiting / Idle Interpreting Opcode
Instruction Flow Sequential (1, 2, 3...) Branching to Address B
ALU No active operation Performing Desired Operation
Destination Undefined Specified Destination Address

đŸ—ēī¸ Visualizing the System OrganizationÂļ

This flowchart visualizes the "Organization of a Stored-program Computer System" shown in Figure 1.2 of your image image_4a6205.jpg.

graph TD
    subgraph CPU
    A[Control Unit] --- B[ALU]
    B --- C[Registers]
    end

    subgraph Memory
    D[Primary Memory] --- E[Secondary Memory]
    end

    subgraph Input_Output
    F[Input Interface] --- G[Input Device/Terminal]
    H[Output Interface] --- I[Output Device/Printer]
    end

    Bus[=== THE SYSTEM BUS ===]

    CPU --- Bus
    Memory --- Bus
    Input_Output --- Bus

alt text

âš ī¸ Important Warnings for BeginnersÂļ

  • âš ī¸ Sequential Warning: āϏāĻžāϧāĻžāϰāĻŖāϤ āĻ•āĻŽā§āĻĒāĻŋāωāϟāĻžāϰ āϏāĻŋāϰāĻŋ⧟āĻžāϞāĻŋ āĻ•āĻžāϜ āĻ•āϰāϞ⧇āĻ“ Branching āĻŦāĻž Subroutine āĻāϰ āϏāĻŽā§Ÿ āĻāϟāĻŋ āϞāĻžāĻĢ āĻĻāĻŋā§Ÿā§‡ āĻ…āĻ¨ā§āϝ āϜāĻžā§ŸāĻ—āĻžā§Ÿ āϚāϞ⧇ āϝ⧇āϤ⧇ āĻĒāĻžāϰ⧇āĨ¤
  • ❌ Memory Confusion: āĻŽāύ⧇ āϰāĻžāĻ–āĻŦ⧇āύ, āχāύāĻ¸ā§āĻŸā§āϰāĻžāĻ•āĻļāύ āĻāĻŦāĻ‚ āĻĄā§‡āϟāĻž āωāϭ⧟āχ āĻ•āĻŋāĻ¨ā§āϤ⧁ āĻāĻ•āχ āĻŽā§‡āĻŽā§‹āϰāĻŋāϤ⧇ āĻĨāĻžāϕ⧇, āϝ⧇ āĻ•āĻžāϰāϪ⧇ āĻāϕ⧇ "Stored-program" āĻ•āĻŽā§āĻĒāĻŋāωāϟāĻžāϰ āĻŦāϞ⧇āĨ¤
  • âš ī¸ The Role of Bus: āφāĻĒāύāĻžāϰ āĻ›āĻŦāĻŋāϰ Figure 1.2 āĻ āϝ⧇ 'Bus' āĻĻ⧇āĻ–āĻž āϝāĻžāĻšā§āϛ⧇, āϏ⧇āϟāĻŋ āĻŽā§‚āϞāϤ āĻāĻ•āϟāĻŋ āĻšāĻžāχāĻ“ā§Ÿā§‡ āϝāĻž CPU, Memory āĻāĻŦāĻ‚ I/O āĻĄāĻŋāĻ­āĻžāχāϏ⧇āϰ āĻŽāĻ§ā§āϝ⧇ āĻĄā§‡āϟāĻž āφāĻĻāĻžāύ-āĻĒā§āϰāĻĻāĻžāύ āĻ•āϰ⧇āĨ¤

ā§§. āĻĄā§‡āĻĄāĻŋāϕ⧇āĻŸā§‡āĻĄ āϰ⧇āϜāĻŋāĻ¸ā§āϟāĻžāϰāϏāĻŽā§‚āĻš (Dedicated Registers)Âļ

CPU-āĻāϰ āĻ•āĻ¨ā§āĻŸā§āϰ⧋āϞ āχāωāύāĻŋāϟ āϤāĻžāϰ āĻ•āĻžāϜāϗ⧁āϞ⧋ āϏāĻŽā§āĻĒāĻ¨ā§āύ āĻ•āϰāĻžāϰ āϜāĻ¨ā§āϝ āϤāĻŋāύāϟāĻŋ āĻĒā§āϰāϧāĻžāύ āϰ⧇āϜāĻŋāĻ¸ā§āϟāĻžāϰ āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻ•āϰ⧇:
* Program Counter (PC): āĻāϟāĻŋ āĻĒāϰāĻŦāĻ°ā§āϤ⧀ āϝ⧇ āχāύāĻ¸ā§āĻŸā§āϰāĻžāĻ•āĻļāύāϟāĻŋ āϚāĻžāϞāĻžāύ⧋ āĻšāĻŦ⧇, āϤāĻžāϰ āĻŽā§‡āĻŽā§‹āϰāĻŋ āĻ…ā§āϝāĻžāĻĄā§āϰ⧇āϏ āϧāϰ⧇ āϰāĻžāϖ⧇āĨ¤
* Instruction Register (IR): āĻŦāĻ°ā§āϤāĻŽāĻžāύ⧇ āϝ⧇ āχāύāĻ¸ā§āĻŸā§āϰāĻžāĻ•āĻļāύāϟāĻŋ āĻĒā§āϰāϏ⧇āϏ āĻ•āϰāĻž āĻšāĻšā§āϛ⧇, āϏ⧇āϟāĻŋ āĻāĻ–āĻžāύ⧇ āĻĨāĻžāϕ⧇āĨ¤
* Effective Address Register (EAR): āĻŽā§‡āĻŽā§‹āϰāĻŋ āĻĨ⧇āϕ⧇ āϝ⧇ āĻĄā§‡āϟāĻž āĻŦāĻž āϤāĻĨā§āϝ āφāύāϤ⧇ āĻšāĻŦ⧇, āϤāĻžāϰ āϏāĻ āĻŋāĻ• āĻ āĻŋāĻ•āĻžāύāĻž āĻāϟāĻŋ āĻŽāύ⧇ āϰāĻžāϖ⧇āĨ¤

âš ī¸ āϏāϤāĻ°ā§āĻ•āϤāĻž: āĻāχ āϰ⧇āϜāĻŋāĻ¸ā§āϟāĻžāϰāϗ⧁āϞ⧋ āϕ⧇āĻŦāϞ āĻ•āĻ¨ā§āĻŸā§āϰ⧋āϞ āχāωāύāĻŋāĻŸā§‡āϰ āϜāĻ¨ā§āϝ āϏāĻ‚āϰāĻ•ā§āώāĻŋāϤāĨ¤ āĻāĻ•āϜāύ āχāωāϜāĻžāϰ āĻŦāĻž āϏāĻžāϧāĻžāϰāĻŖ āĻĒā§āϰ⧋āĻ—ā§āϰāĻžāĻŽāĻžāϰ āϏāϰāĻžāϏāϰāĻŋ āĻāϗ⧁āϞ⧋ āĻāĻ•ā§āϏ⧇āϏ āĻ•āϰāϤ⧇ āĻĒāĻžāϰ⧇ āύāĻžāĨ¤

⧍. āĻ•āĻ¨ā§āĻŸā§āϰ⧋āϞ āĻĢā§āϞ⧋ (Control Flow Sequences)Âļ

āĻ•āĻŽā§āĻĒāĻŋāωāϟāĻžāϰ āϏāĻžāϧāĻžāϰāĻŖāϤ āĻŽā§‡āĻŽā§‹āϰāĻŋ āĻĨ⧇āϕ⧇ āϏāĻŋāϰāĻŋ⧟āĻžāϞāĻŋ āĻ•āĻžāϜ āĻ•āϰ⧇, āĻ•āĻŋāĻ¨ā§āϤ⧁ image_496a64.jpg āĻāϰ Figure 1.3 āĻ āĻĻ⧁āϟāĻŋ āĻŦā§āϝāϤāĻŋāĻ•ā§āϰāĻŽ āĻĻ⧇āĻ–āĻžāύ⧋ āĻšā§Ÿā§‡āϛ⧇:
* Branch Instruction (Figure 1.3a): āϝāĻ–āύ āĻŽā§‡āĻŽā§‹āϰāĻŋ āϞ⧋āϕ⧇āĻļāύ ā§Ē āĻĨ⧇āϕ⧇ āϏāϰāĻžāϏāϰāĻŋ āϞ⧋āϕ⧇āĻļāύ B-āϤ⧇ āϞāĻžāĻĢ āĻĻ⧇āĻ“ā§ŸāĻž āĻšā§ŸāĨ¤
* Subroutine Call (Figure 1.3b): āϝāĻ–āύ āĻŽā§‚āϞ āĻĒā§āϰ⧋āĻ—ā§āϰāĻžāĻŽ āĻĨāĻžāĻŽāĻŋā§Ÿā§‡ āĻ…āĻ¨ā§āϝ āĻāĻ•āϟāĻŋ āϛ⧋āϟ āĻĒā§āϰ⧋āĻ—ā§āϰāĻžāĻŽ (Subprogram) āϚāĻžāϞāĻžāύ⧋ āĻšā§Ÿ āĻāĻŦāĻ‚ āĻ•āĻžāϜ āĻļ⧇āώ⧇ 'Return' āχāύāĻ¸ā§āĻŸā§āϰāĻžāĻ•āĻļāύ⧇āϰ āĻŽāĻžāĻ§ā§āϝāĻŽā§‡ āφāĻŦāĻžāϰ āφāϗ⧇āϰ āϜāĻžā§ŸāĻ—āĻžā§Ÿ āĻĢāĻŋāϰ⧇ āφāϏāĻž āĻšā§ŸāĨ¤

🧠 āĻŽā§‡āĻŽā§‹āϰāĻŋ āχāωāύāĻŋāϟ (Memory Unit Overview)Âļ

āĻ•āĻŽā§āĻĒāĻŋāωāϟāĻžāϰ⧇āϰ āϏāĻŦ āĻĒā§āϰ⧋āĻ—ā§āϰāĻžāĻŽ āĻāĻŦāĻ‚ āĻĄā§‡āϟāĻž āĻŽā§‡āĻŽā§‹āϰāĻŋāϤ⧇ āϜāĻŽāĻž āĻĨāĻžāϕ⧇āĨ¤ āĻāχ āĻŽā§‡āĻŽā§‹āϰāĻŋāϕ⧇ āĻŽā§‚āϞāϤ āĻĻ⧁āϟāĻŋ āĻ­āĻžāϗ⧇ āĻ­āĻžāĻ— āĻ•āϰāĻž āϝāĻžā§Ÿ:

  • Primary Memory: āĻāϟāĻŋ āϏāϞāĻŋāĻĄ-āĻ¸ā§āĻŸā§‡āϟ āĻĒā§āϰāϝ⧁āĻ•ā§āϤāĻŋāϤ⧇ āϤ⧈āϰāĻŋ āĻāĻŦāĻ‚ āĻāϕ⧇ 'Executable Memory' āĻŦāϞāĻž āĻšā§Ÿ āĻ•āĻžāϰāĻŖ CPU āϏāϰāĻžāϏāϰāĻŋ āĻāĻ–āĻžāύ āĻĨ⧇āϕ⧇ āĻ•āĻžāϜ āĻ•āϰāϤ⧇ āĻĒāĻžāϰ⧇āĨ¤
  • Secondary Memory: āĻāϟāĻŋ āĻŽā§‚āϞāϤ āĻŽā§āϝāĻžāĻ—āύ⧇āϟāĻŋāĻ• āĻĄāĻŋāĻ¸ā§āĻ• āĻŦāĻž āĻŸā§‡āĻĒ āϜāĻžāĻ¤ā§€ā§Ÿ āχāϞ⧇āĻ•āĻŸā§āϰ⧋āĻŽā§‡āĻ•āĻžāύāĻŋāĻ•ā§āϝāĻžāϞ āĻĄāĻŋāĻ­āĻžāχāϏāĨ¤

📊 Quick Sneak Peak: Primary vs SecondaryÂļ

Feature Primary Memory Secondary Memory
Technology Solid-state Electromechanical (Disks/Tapes)
Speed Very Fast (Matches CPU) Slow
Cost High Low
CPU Access Directly executable Indirect (Needs swapping)

💾 āĻĒā§āϰāĻžāχāĻŽāĻžāϰāĻŋ āĻŽā§‡āĻŽā§‹āϰāĻŋ: RWM āĻŦāύāĻžāĻŽ ROMÂļ

āĻĒā§āϰāĻžāχāĻŽāĻžāϰāĻŋ āĻŽā§‡āĻŽā§‹āϰāĻŋ āφāĻŦāĻžāϰ āĻĻ⧁āχ āϧāϰāϪ⧇āϰ āĻšā§Ÿ:

  1. Read-Write Memory (RWM): āĻāĻ–āĻžāύ⧇ āφāĻĒāύāĻŋ āĻĄā§‡āϟāĻž āĻĒ⧜āϤ⧇āĻ“ āĻĒāĻžāϰāĻŦ⧇āύ āĻāĻŦāĻ‚ āύāϤ⧁āύ āĻ•āĻŋāϛ⧁ āϞāĻŋāĻ–āϤ⧇āĻ“ āĻĒāĻžāϰāĻŦ⧇āύāĨ¤
  2. Read-Only Memory (ROM): āĻāĻ–āĻžāύ āĻĨ⧇āϕ⧇ āĻļ⧁āϧ⧁ āĻĄā§‡āϟāĻž āĻĒ⧜āĻž āϝāĻžā§ŸāĨ¤ āϕ⧇āύ āφāĻŽāϰāĻž ROM āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻ•āϰāĻŋ?
    • 💰 Low Price: āĻŦāĻ°ā§āϤāĻŽāĻžāύ⧇ āϏāĻ¸ā§āϤāĻžā§Ÿ ROM āϤ⧈āϰāĻŋ āĻ•āϰāĻž āϝāĻžā§ŸāĨ¤
    • 🔒 Permanent Info: āĻ•āĻŋāϛ⧁ āϤāĻĨā§āϝ āϝ⧇āĻŽāύ āĻŽāύāĻŋāϟāϰ āĻĒā§āϰ⧋āĻ—ā§āϰāĻžāĻŽ āĻŦāĻž āĻŽā§āϝāĻžāĻĨāĻŽā§‡āϟāĻŋāĻ•ā§āϝāĻžāϞ āĻŸā§‡āĻŦāĻŋāϞ āĻ•āĻ–āύ⧋āχ āĻŦāĻĻāϞāĻžāύ⧋āϰ āĻĒā§āĻ°ā§Ÿā§‹āϜāύ āĻšā§Ÿ āύāĻžāĨ¤

âš ī¸ Warning: RWM āĻāĻŦāĻ‚ ROM āωāϭ⧟āϕ⧇āχ 'Random-Access' āĻĄāĻŋāĻ­āĻžāχāϏ āĻŦāϞāĻž āĻšā§Ÿ āĻ•āĻžāϰāĻŖ āĻŽā§‡āĻŽā§‹āϰāĻŋāϰ āϝ⧇āϕ⧋āύ⧋ āϜāĻžā§ŸāĻ—āĻž āĻĨ⧇āϕ⧇ āĻĄā§‡āϟāĻž āφāύāϤ⧇ āĻāĻ•āχ āϏāĻŽā§Ÿ āϞāĻžāϗ⧇āĨ¤

āφāϏāϞ⧇ āφāĻĒāύāĻŋ āĻāϤāĻ•ā§āώāĻŖ āϝ⧇ Read-Write Memory (RWM) āϏāĻŽā§āĻĒāĻ°ā§āϕ⧇ āϜāĻžāύāĻ›āĻŋāϞ⧇āύ, āϏ⧇āϟāĻŋāχ āĻšāϞ⧋ RAM (Random Access Memory)āĨ¤

āϏāĻšāϜ āĻ•āĻĨāĻžā§Ÿ, RAM āĻšāϞ⧋ āĻ•āĻŽā§āĻĒāĻŋāωāϟāĻžāϰ⧇āϰ "āĻāĻ•ā§āϟāĻŋāĻ­ āĻ•āĻžāĻœā§‡āϰ āĻŸā§‡āĻŦāĻŋāϞ"āĨ¤ āφāĻĒāύāĻžāϰ āĻŦāĻ‡ā§Ÿā§‡āϰ āĻĒāĻžāϤāĻž (image_4904cb.jpg) āĻ…āύ⧁āϝāĻžā§Ÿā§€, āĻāϟāĻŋ āĻāĻŽāύ āĻāĻ• āϧāϰāϪ⧇āϰ āĻĒā§āϰāĻžāχāĻŽāĻžāϰāĻŋ āĻŽā§‡āĻŽā§‹āϰāĻŋ āϝ⧇āĻ–āĻžāύ⧇ āϤāĻĨā§āϝ āĻĒ⧜āĻž āĻāĻŦāĻ‚ āϞ⧇āĻ–āĻžâ€”āωāϭ⧟āχ āĻ•āϰāĻž āϝāĻžā§ŸāĨ¤

āϕ⧇āύ āĻāϕ⧇ RAM āĻŦāϞ⧇? āĻ•āĻžāϰāĻŖ āĻŽā§‡āĻŽā§‹āϰāĻŋāϰ āϝ⧇āϕ⧋āύ⧋ āϜāĻžā§ŸāĻ—āĻž (Address) āĻĨ⧇āϕ⧇ āϤāĻĨā§āϝ āϏāĻ‚āĻ—ā§āϰāĻš āĻ•āϰāϤ⧇ āĻāĻ•āĻĻāĻŽ āϏāĻŽāĻžāύ āϏāĻŽā§Ÿ āϞāĻžāϗ⧇, āϝāĻžāϕ⧇ āĻŦāĻ‡ā§Ÿā§‡ 'Random-access' āĻŦāϞāĻž āĻšā§Ÿā§‡āϛ⧇āĨ¤

āĻ­ā§‹āĻ˛ā§āϟāĻžāχāϞ āĻŽā§‡āĻŽā§‹āϰāĻŋ: RAM-āĻāϰ āϏāĻŦāĻšā§‡ā§Ÿā§‡ āĻŦ⧜ āĻŦ⧈āĻļāĻŋāĻˇā§āĻŸā§āϝ āĻšāϞ⧋ āĻāϟāĻŋ āĻ…āĻ¸ā§āĻĨāĻžā§Ÿā§€āĨ¤ āĻŦāĻŋāĻĻā§āĻ¯ā§ā§Ž āϚāϞ⧇ āϗ⧇āϞ⧇ āĻāϰ āϏāĻŦ āϤāĻĨā§āϝ āĻŽā§āϛ⧇ āϝāĻžā§ŸāĨ¤ āϤāĻžāχ āĻāϕ⧇ āϏāĻ‚āϰāĻ•ā§āώāĻŋāϤ āĻŦāĻž āĻ¸ā§āĻĨāĻžā§Ÿā§€ āϤāĻĨā§āϝ⧇āϰ āϜāĻ¨ā§āϝ āĻŦā§āϝāĻŦāĻšāĻžāϰ āĻ•āϰāĻž āĻšā§Ÿ āύāĻžāĨ¤

āĻ•āĻžāĻœā§‡āϰ āϧāϰāĻŖ: āφāĻĒāύāĻŋ āϝāĻ–āύ āϕ⧋āύ⧋ āĻ…ā§āϝāĻžāĻĒ āĻŦāĻž āϗ⧇āĻŽ āĻ“āĻĒ⧇āύ āĻ•āϰ⧇āύ, āϏ⧇āϟāĻŋ āϏ⧇āϕ⧇āĻ¨ā§āĻĄāĻžāϰāĻŋ āĻŽā§‡āĻŽā§‹āϰāĻŋ (āϝ⧇āĻŽāύ: SSD āĻŦāĻž Hard Disk) āĻĨ⧇āϕ⧇ āϞāĻžāĻĢ āĻĻāĻŋā§Ÿā§‡ RAM-āĻ āϚāϞ⧇ āφāϏ⧇ āϝāĻžāϤ⧇ CPU āĻĻā§āϰ⧁āϤ āϏ⧇āϟāĻŋ āĻāĻ•ā§āϏ⧇āϏ āĻ•āϰāϤ⧇ āĻĒāĻžāϰ⧇āĨ¤

āφāĻĒāύāĻžāϰ āĻļā§‡ā§ŸāĻžāϰ āĻ•āϰāĻž image_4c7d03.jpg āĻĢāĻžāχāϞāϟāĻŋāϤ⧇ āĻ•āĻŽā§āĻĒāĻŋāωāϟāĻžāϰ⧇āϰ āϝ⧋āĻ—āĻžāϝ⧋āϗ⧇āϰ āϰāĻžāĻ¸ā§āϤāĻž āĻ…āĻ°ā§āĻĨāĻžā§Ž System Bus āĻāĻŦāĻ‚ āĻ•āĻŽā§āĻĒāĻŋāωāϟāĻžāϰ⧇āϰ āĻ—āĻ āύ āĻŦāĻž Structures āύāĻŋā§Ÿā§‡ āφāϞ⧋āϚāύāĻž āĻ•āϰāĻž āĻšā§Ÿā§‡āϛ⧇āĨ¤ āϚāϞ⧁āύ āĻāĻ•āĻĻāĻŽ āĻ—ā§‹ā§œāĻž āĻĨ⧇āϕ⧇ āĻāϟāĻŋ āĻŦ⧁āĻā§‡ āύ⧇āĻ“ā§ŸāĻž āϝāĻžāĻ•āĨ¤Âļ

ā§§. āϏāĻŋāĻ¸ā§āĻŸā§‡āĻŽ āĻŦāĻžāϏ (The System Bus) 🚌Âļ

āĻ•āĻŽā§āĻĒāĻŋāωāϟāĻžāϰ⧇āϰ āĻŦāĻŋāĻ­āĻŋāĻ¨ā§āύ āĻ…āĻ‚āĻļ āϝ⧇ āϤāĻžāϰ⧇āϰ āĻŽāĻžāĻ§ā§āϝāĻŽā§‡ āĻāϕ⧇ āĻ…āĻĒāϰ⧇āϰ āϏāĻžāĻĨ⧇ āĻ•āĻĨāĻž āĻŦāϞ⧇, āϤāĻžāϕ⧇āχ Bus āĻŦāϞ⧇āĨ¤ āĻāϟāĻŋ āϤāĻŋāύ āĻĒā§āϰāĻ•āĻžāϰ:
* Address Bus: āĻāϟāĻŋ āϕ⧇āĻŦāϞ āĻāĻ•āĻŽā§āĻ–ā§€ (Unidirectional)āĨ¤ āĻĒā§āϰāϏ⧇āϏāϰ āϕ⧋āύ āĻŽā§‡āĻŽā§‹āϰāĻŋ āĻŦāĻž āĻĄāĻŋāĻ­āĻžāχāϏ⧇āϰ āϏāĻžāĻĨ⧇ āĻ•āĻžāϜ āĻ•āϰāĻŦ⧇, āϤāĻžāϰ āĻ āĻŋāĻ•āĻžāύāĻž āĻŦāĻž āĻ…ā§āϝāĻžāĻĄā§āϰ⧇āϏ āĻāϟāĻŋ āĻĻāĻŋā§Ÿā§‡ āĻĒāĻžāĻ āĻžā§ŸāĨ¤ ā§Šā§¨-āĻŦāĻŋāĻŸā§‡āϰ āĻŦāĻžāϏ āĻšāϞ⧇ āĻāϟāĻŋ ā§Ē āĻŦāĻŋāϞāĻŋ⧟āύ⧇āϰ āĻŦ⧇āĻļāĻŋ āϜāĻžā§ŸāĻ—āĻž āϖ⧁āρāĻœā§‡ āĻĒ⧇āϤ⧇ āĻĒāĻžāϰ⧇āĨ¤
* Data Bus: āĻāϟāĻŋ āωāĻ­āĻŽā§āĻ–ā§€ (Bidirectional)āĨ¤ āĻĒā§āϰāϏ⧇āϏāϰ āĻāĻŦāĻ‚ āĻŽā§‡āĻŽā§‹āϰāĻŋāϰ āĻŽāĻ§ā§āϝ⧇ āϤāĻĨā§āϝ āφāĻĻāĻžāύ-āĻĒā§āϰāĻĻāĻžāύ āĻ•āϰāĻžāϰ āϰāĻžāĻ¸ā§āϤāĻž āĻāϟāĻŋāĨ¤
* Control Bus: āĻāϟāĻŋ āĻŸā§āϰāĻžāĻĢāĻŋāĻ• āĻĒ⧁āϞāĻŋāĻļ⧇āϰ āĻŽāϤ⧋āĨ¤ āĻāϟāĻŋ āύāĻŋāĻ°ā§āĻĻ⧇āĻļ āĻĻā§‡ā§Ÿ āϝ⧇ āĻāĻ–āύ āĻĄā§‡āϟāĻž āĻĒ⧜āĻž āĻšāĻŦ⧇ āύāĻžāĻ•āĻŋ āϞ⧇āĻ–āĻž āĻšāĻŦ⧇ āĻāĻŦāĻ‚ āϏāĻŦ āĻĄāĻŋāĻ­āĻžāχāϏāϕ⧇ āϏāĻŋāύāĻ•ā§āϰ⧋āύāĻžāχāϜ āĻ•āϰ⧇āĨ¤

⧍. āĻ•āĻŽā§āĻĒāĻŋāωāϟāĻžāϰ āĻ¸ā§āĻŸā§āϰāĻžāĻ•āϚāĻžāϰ (Computer Structures) đŸ—ī¸Âļ

āĻ•āĻŽā§āĻĒāĻŋāωāϟāĻžāϰāϗ⧁āϞ⧋ āϕ⧀āĻ­āĻžāĻŦ⧇ āĻĄā§‡āϟāĻž āĻĒā§āϰāϏ⧇āϏ āĻ•āϰ⧇, āϤāĻžāϰ āĻ“āĻĒāϰ āĻ­āĻŋāĻ¤ā§āϤāĻŋ āĻ•āϰ⧇ āĻāĻĻ⧇āϰ āϤāĻŋāύ āĻ­āĻžāϗ⧇ āĻ­āĻžāĻ— āĻ•āϰāĻž āĻšā§Ÿā§‡āϛ⧇:
* General Register Machines: āĻāĻ–āĻžāύ⧇ āĻ…āύ⧇āĻ•āϗ⧁āϞ⧋ āĻĒāϕ⧇āϟ āĻŦāĻž āϰ⧇āϜāĻŋāĻ¸ā§āϟāĻžāϰ (\(R_0\) āĻĨ⧇āϕ⧇ \(R_7\)) āĻĨāĻžāϕ⧇ āĻĄā§‡āϟāĻž āϰāĻžāĻ–āĻžāϰ āϜāĻ¨ā§āϝāĨ¤
* Accumulator Based Machines: āĻāĻ–āĻžāύ⧇ āĻāĻ•āϟāĻŋ āĻĒā§āϰāϧāĻžāύ āϰ⧇āϜāĻŋāĻ¸ā§āϟāĻžāϰ āĻĨāĻžāϕ⧇ āϝāĻž āĻĻāĻŋā§Ÿā§‡ āϏāĻŦ āĻ•āĻžāϜ āĻšā§ŸāĨ¤
* Stack Machines: āĻāϟāĻŋ āĻāĻ•āϟāĻŋ āĻĨāĻžāϞāĻžāϰ āĻ¸ā§āϤ⧂āĻĒ⧇āϰ āĻŽāϤ⧋ āĻ•āĻžāϜ āĻ•āϰ⧇āĨ¤

âš ī¸ āĻŽāύ⧇ āϰāĻžāĻ–āĻŦ⧇āύ: Flag Register (F) āϖ⧁āĻŦ āϗ⧁āϰ⧁āĻ¤ā§āĻŦāĻĒā§‚āĻ°ā§āĻŖāĨ¤ āĻāϟāĻŋ āĻŦāϞ⧇ āĻĻā§‡ā§Ÿ āϕ⧋āύ⧋ āϝ⧋āĻ—āĻĢāϞ āĻ•āĻŋ āĻļā§‚āĻ¨ā§āϝ āĻšā§Ÿā§‡āϛ⧇ (Z-flag) āύāĻžāĻ•āĻŋ āĻšāĻžāϤ⧇ āĻ•āĻŋāϛ⧁ āĻ°ā§Ÿā§‡ āϗ⧇āϛ⧇ (Carry flag)āĨ¤

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āφāĻĒāύāĻžāϰ āĻĻ⧇āĻ“ā§ŸāĻž āĻ›āĻŦāĻŋāϟāĻŋ āĻāĻ•āϟāĻŋ āϏāĻžāϧāĻžāϰāĻŖ āϰ⧇āϜāĻŋāĻ¸ā§āϟāĻžāϰ āĻĒā§āϰāϏ⧇āϏāϰ⧇āϰ (General Register Processor) āĻ—āĻ āύ āĻŦāĻž āφāĻ°ā§āĻ•āĻŋāĻŸā§‡āĻ•āϚāĻžāϰ āϤ⧁āϞ⧇ āϧāϰāϛ⧇āĨ¤ āύāĻŋāĻšā§‡ āĻĄāĻžā§ŸāĻžāĻ—ā§āϰāĻžāĻŽā§‡āϰ āĻĒā§āϰāϤāĻŋāϟāĻŋ āĻ…āĻ‚āĻļ⧇āϰ āĻŦāĻŋāĻ¸ā§āϤāĻžāϰāĻŋāϤ āĻŦā§āϝāĻžāĻ–ā§āϝāĻž āĻŦāĻžāĻ‚āϞāĻžā§Ÿ āĻĻ⧇āĻ“ā§ŸāĻž āĻšāϞ⧋:

āϚāĻŋāĻ¤ā§āϰ ā§§.ā§Ē: āĻāĻ•āϟāĻŋ āϏāĻžāϧāĻžāϰāĻŖ āϰ⧇āϜāĻŋāĻ¸ā§āϟāĻžāϰ āĻĒā§āϰāϏ⧇āϏāϰ⧇āϰ āĻ—āĻ āύ (Organization of a Typical General Register Processor)Âļ

āĻāχ āĻĄāĻžā§ŸāĻžāĻ—ā§āϰāĻžāĻŽāϟāĻŋ āĻŽā§‚āϞāϤ āĻĒā§āϰāϏ⧇āϏāϰ⧇āϰ āϭ⧇āϤāϰ⧇āϰ āĻŦāĻŋāĻ­āĻŋāĻ¨ā§āύ āĻ…āĻ‚āĻļ āĻāĻŦāĻ‚ āϤāĻžāϰāĻž āϕ⧀āĻ­āĻžāĻŦ⧇ āĻāϕ⧇ āĻ…āĻĒāϰ⧇āϰ āϏāĻžāĻĨ⧇ āϝ⧁āĻ•ā§āϤ āĻĨāĻžāϕ⧇ āϤāĻž āĻĻ⧇āĻ–āĻžā§ŸāĨ¤


ā§§. āĻœā§‡āύāĻžāϰ⧇āϞ āϰ⧇āϜāĻŋāĻ¸ā§āϟāĻžāϰ (General Registers: R0 - R7)Âļ

  • āĻāĻ–āĻžāύ⧇ āĻŽā§‹āϟ ā§ŽāϟāĻŋ āϏāĻžāϧāĻžāϰāĻŖ āϰ⧇āϜāĻŋāĻ¸ā§āϟāĻžāϰ āĻ°ā§Ÿā§‡āϛ⧇ (R0 āĻĨ⧇āϕ⧇ R7)āĨ¤
  • āĻ•āĻžāϜ: āĻāϗ⧁āϞ⧋ āĻĄā§‡āϟāĻž, āĻŽā§‡āĻŽā§‹āϰāĻŋ āĻ…ā§āϝāĻžāĻĄā§āϰ⧇āϏ āĻ…āĻĨāĻŦāĻž āϕ⧋āύ⧋ āĻ—āĻžāĻŖāĻŋāϤāĻŋāĻ• āĻŦāĻž āϞāϜāĻŋāĻ•ā§āϝāĻžāϞ āĻ…āĻĒāĻžāϰ⧇āĻļāύ⧇āϰ āĻĢāϞāĻžāĻĢāϞ āϏāĻžāĻŽā§ŸāĻŋāĻ•āĻ­āĻžāĻŦ⧇ āϜāĻŽāĻž āϰāĻžāĻ–āĻžāϰ āϜāĻ¨ā§āϝ āĻŦā§āϝāĻŦāĻšā§ƒāϤ āĻšā§ŸāĨ¤

⧍. PC (Program Counter)Âļ

  • āĻ•āĻžāϜ: āĻĒā§āϰāϏ⧇āϏāϰ āĻŦāĻ°ā§āϤāĻŽāĻžāύ⧇ āϝ⧇ āύāĻŋāĻ°ā§āĻĻ⧇āĻļāϟāĻŋ (Instruction) āĻĒāĻžāϞāύ āĻ•āϰāϛ⧇, āϤāĻžāϰ āĻ āĻŋāĻ• āĻĒāϰ⧇āϰ āύāĻŋāĻ°ā§āĻĻ⧇āĻļ⧇āϰ āĻŽā§‡āĻŽā§‹āϰāĻŋ āĻ…ā§āϝāĻžāĻĄā§āϰ⧇āϏ āĻŦāĻž āĻ āĻŋāĻ•āĻžāύāĻž āĻāχ āϰ⧇āϜāĻŋāĻ¸ā§āϟāĻžāϰ⧇ āϜāĻŽāĻž āĻĨāĻžāϕ⧇āĨ¤ āĻāϟāĻŋ āĻ•āĻŽā§āĻĒāĻŋāωāϟāĻžāϰāϕ⧇ āĻĒāϰāĻŦāĻ°ā§āϤ⧀ āĻ•āĻžāĻœā§‡āϰ āĻĻāĻŋāĻ•āύāĻŋāĻ°ā§āĻĻ⧇āĻļāύāĻž āĻĻā§‡ā§ŸāĨ¤

ā§Š. EAR (Effective Address Register)Âļ

  • āĻ•āĻžāϜ: āĻŽā§‡āĻŽā§‹āϰāĻŋ āĻĨ⧇āϕ⧇ āϝāĻ–āύ āϕ⧋āύ⧋ āĻĄā§‡āϟāĻž āύāĻŋāϤ⧇ āĻŦāĻž āĻĒāĻžāĻ āĻžāϤ⧇ āĻšā§Ÿ, āϤāĻ–āύ āϏ⧇āχ āύāĻŋāĻ°ā§āĻĻāĻŋāĻˇā§āϟ āĻŽā§‡āĻŽā§‹āϰāĻŋ āϞ⧋āϕ⧇āĻļāύ⧇āϰ āĻ…ā§āϝāĻžāĻĄā§āϰ⧇āϏ āĻāχ āϰ⧇āϜāĻŋāĻ¸ā§āϟāĻžāϰ⧇ āϏāĻ‚āϰāĻ•ā§āώāĻŋāϤ āĻĨāĻžāϕ⧇āĨ¤

ā§Ē. SP (Stack Pointer)Âļ

  • āĻāϟāĻŋ āĻāĻ•āϟāĻŋ āĻŦāĻŋāĻļ⧇āώ āĻŦāĻž āĻĄā§‡āĻĄāĻŋāϕ⧇āĻŸā§‡āĻĄ āϰ⧇āϜāĻŋāĻ¸ā§āϟāĻžāϰāĨ¤
  • āĻ•āĻžāϜ: āĻāϟāĻŋ āĻŽā§‡āĻŽā§‹āϰāĻŋāϰ āĻāĻ•āϟāĻŋ āĻŦāĻŋāĻļ⧇āώ āĻ…āĻ‚āĻļ 'āĻ¸ā§āĻŸā§āϝāĻžāĻ•'-āĻāϰ āĻāĻ•āĻĻāĻŽ āωāĻĒāϰ⧇āϰ āĻāϞāĻŋāĻŽā§‡āĻ¨ā§āĻŸā§‡āϰ āĻ āĻŋāĻ•āĻžāύāĻž āĻŦāĻž āĻ…ā§āϝāĻžāĻĄā§āϰ⧇āϏ āϧāϰ⧇ āϰāĻžāϖ⧇āĨ¤

ā§Ģ. IR (Instruction Register) āĻ“ āĻ•āĻ¨ā§āĻŸā§āϰ⧋āϞ āχāωāύāĻŋāϟ (Control Unit)Âļ

  • IR: āĻĒā§āϰāϏ⧇āϏāϰ āĻŦāĻ°ā§āϤāĻŽāĻžāύ⧇ āϝ⧇ āύāĻŋāĻ°ā§āĻĻ⧇āĻļāϟāĻŋ āύāĻŋā§Ÿā§‡ āĻ•āĻžāϜ āĻ•āϰāϛ⧇, āϏ⧇āϟāĻŋ āĻāĻ–āĻžāύ⧇ āĻĨāĻžāϕ⧇āĨ¤
  • āĻ•āĻ¨ā§āĻŸā§āϰ⧋āϞ āχāωāύāĻŋāϟ: āĻāϟāĻŋ āĻĒā§āϰāϏ⧇āϏāϰ⧇āϰ 'āĻŽāĻ¸ā§āϤāĻŋāĻˇā§āĻ•' āĻšāĻŋāϏ⧇āĻŦ⧇ āĻ•āĻžāϜ āĻ•āϰ⧇āĨ¤ āĻāϟāĻŋ IR āĻĨ⧇āϕ⧇ āύāĻŋāĻ°ā§āĻĻ⧇āĻļ āĻĒā§œā§‡ āĻāĻŦāĻ‚ āϏ⧇āχ āĻ…āύ⧁āϝāĻžā§Ÿā§€ ALU āĻ“ āĻ…āĻ¨ā§āϝāĻžāĻ¨ā§āϝ āĻ…āĻ‚āĻļāϕ⧇ āĻ•āĻžāϜ āĻ•āϰāĻžāϰ āϏāĻŋāĻ—āĻ¨ā§āϝāĻžāϞ āĻĻā§‡ā§ŸāĨ¤

ā§Ŧ. ALU (Arithmetic Logic Unit)Âļ

  • āĻ•āĻžāϜ: āĻ•āĻŽā§āĻĒāĻŋāωāϟāĻžāϰ⧇āϰ āϝāĻžāĻŦāĻ¤ā§€ā§Ÿ āĻ—āĻžāĻŖāĻŋāϤāĻŋāĻ• āĻ•āĻžāϜ (āϝ⧇āĻŽāύ: āϝ⧋āĻ—, āĻŦāĻŋā§Ÿā§‹āĻ—, āϗ⧁āĻŖ, āĻ­āĻžāĻ—) āĻāĻŦāĻ‚ āϝ⧌āĻ•ā§āϤāĻŋāĻ• āĻŦāĻž āϞāϜāĻŋāĻ•ā§āϝāĻžāϞ āĻ•āĻžāϜ āĻāχ āĻ…āĻ‚āĻļ⧇ āϏāĻŽā§āĻĒāĻ¨ā§āύ āĻšā§ŸāĨ¤ āĻĄāĻžā§ŸāĻžāĻ—ā§āϰāĻžāĻŽā§‡ āĻĻ⧇āĻ–āĻž āϝāĻžāĻšā§āϛ⧇, āĻœā§‡āύāĻžāϰ⧇āϞ āϰ⧇āϜāĻŋāĻ¸ā§āϟāĻžāϰ āĻĨ⧇āϕ⧇ āĻĄā§‡āϟāĻž āϏāϰāĻžāϏāϰāĻŋ ALU-āϤ⧇ āĻĒā§āϰāĻŦāĻžāĻšāĻŋāϤ āĻšāĻšā§āϛ⧇āĨ¤

ā§­. F (Flag Register)Âļ

  • āĻāϕ⧇ āĻ¸ā§āĻŸā§āϝāĻžāϟāĻžāϏ āϰ⧇āϜāĻŋāĻ¸ā§āϟāĻžāϰ āĻŦāĻž āĻĢā§āĻ˛ā§āϝāĻžāĻ— āϰ⧇āϜāĻŋāĻ¸ā§āϟāĻžāϰ āĻŦāϞāĻž āĻšā§ŸāĨ¤
  • āĻ•āĻžāϜ: āĻāϟāĻŋ ALU-āϤ⧇ āĻ•āϰāĻž āϕ⧋āύ⧋ āĻ…āĻĒāĻžāϰ⧇āĻļāύ⧇āϰ āĻĢāϞāĻžāĻĢāϞ āĻŦāĻž āĻ…āĻŦāĻ¸ā§āĻĨāĻžāϰ āϤāĻĨā§āϝ āĻĻā§‡ā§ŸāĨ¤ āϝ⧇āĻŽāύ: āϝāĻĻāĻŋ āϕ⧋āύ⧋ āĻšāĻŋāϏāĻžāĻŦ⧇āϰ āĻĢāϞāĻžāĻĢāϞ āĻļā§‚āĻ¨ā§āϝ (Zero) āĻšā§Ÿ, āϤāĻŦ⧇ āĻāϰ Z-flag ā§§ āĻšā§Ÿā§‡ āϝāĻžā§ŸāĨ¤ āĻāϤ⧇ āĻ•ā§āϝāĻžāϰāĻŋ āĻĢā§āĻ˛ā§āϝāĻžāĻ— (Carry flag)-āĻ“ āĻĨāĻžāϕ⧇āĨ¤

ā§Ž. Memory and I/O InterfaceÂļ

  • āĻ•āĻžāϜ: āĻāχ āĻ…āĻ‚āĻļ⧇āϰ āĻŽāĻžāĻ§ā§āϝāĻŽā§‡ āĻĒā§āϰāϏ⧇āϏāϰ āĻ•āĻŽā§āĻĒāĻŋāωāϟāĻžāϰ⧇āϰ āĻŽā§‚āϞ āĻŽā§‡āĻŽā§‹āϰāĻŋ (RAM) āĻāĻŦāĻ‚ āĻŦāĻŋāĻ­āĻŋāĻ¨ā§āύ āχāύāĻĒ⧁āϟ/āφāωāϟāĻĒ⧁āϟ āĻĄāĻŋāĻ­āĻžāχāϏ⧇āϰ (āϝ⧇āĻŽāύ- āĻ•āĻŋāĻŦā§‹āĻ°ā§āĻĄ, āĻĄāĻŋāϏāĻĒā§āϞ⧇) āϏāĻžāĻĨ⧇ āϝ⧋āĻ—āĻžāϝ⧋āĻ— āĻ•āϰ⧇āĨ¤

⧝. āĻĄā§‡āϟāĻž āĻ“ āĻ…ā§āϝāĻžāĻĄā§āϰ⧇āϏ āĻĒāĻžāĻĨ (Arrows/Buses)Âļ

  • āĻĄāĻžā§ŸāĻžāĻ—ā§āϰāĻžāĻŽā§‡āϰ āϤ⧀āϰ āϚāĻŋāĻšā§āύāϗ⧁āϞ⧋ āĻŽā§‚āϞāϤ āϤāĻĨā§āϝ āϚāϞāĻžāϚāϞ⧇āϰ āĻĒāĻĨ āĻŦāĻž 'āĻŦāĻžāϏ' (Bus) āύāĻŋāĻ°ā§āĻĻ⧇āĻļ āĻ•āϰ⧇āĨ¤ āĻāχ āĻĒāĻĨāϗ⧁āϞ⧋ āĻĻāĻŋā§Ÿā§‡āχ āĻĄā§‡āϟāĻž āĻāĻŦāĻ‚ āĻ…ā§āϝāĻžāĻĄā§āϰ⧇āϏ āĻŦāĻŋāĻ­āĻŋāĻ¨ā§āύ āϰ⧇āϜāĻŋāĻ¸ā§āϟāĻžāϰ āĻ“ āĻŽā§‡āĻŽā§‹āϰāĻŋāϰ āĻŽāĻ§ā§āϝ⧇ āφāĻĻāĻžāύ-āĻĒā§āϰāĻĻāĻžāύ āĻ•āϰāĻž āĻšā§ŸāĨ¤

āϏāĻ‚āĻ•ā§āώ⧇āĻĒ⧇ āύāĻŋāĻ°ā§āĻĻ⧇āĻļ⧇āϰ āϧāϰāύ (Instruction Types):
āĻāχ āϧāϰāύ⧇āϰ āĻĒā§āϰāϏ⧇āϏāϰ āϏāĻžāϧāĻžāϰāĻŖāϤ āĻĻ⧁āχ āϧāϰāύ⧇āϰ āύāĻŋāĻ°ā§āĻĻ⧇āĻļ āϏāĻŽāĻ°ā§āĻĨāύ āĻ•āϰ⧇:
* Three-address instructions: āϝ⧇āĻŽāύ ADD x, y, z (āĻāĻ–āĻžāύ⧇ x āĻāĻŦāĻ‚ y āϝ⧋āĻ— āĻ•āϰ⧇ āĻĢāϞāĻžāĻĢāϞ z-āĻ āϰāĻžāĻ–āĻž āĻšā§Ÿ)āĨ¤
* Two-address instructions: āϝ⧇āĻŽāύ MOV x, y (āĻāĻ–āĻžāύ⧇ x-āĻāϰ āĻŽāĻžāύ y-āϤ⧇ āĻ•āĻĒāĻŋ āĻ•āϰāĻž āĻšā§Ÿ)āĨ¤


Accumulator Based Processor (English)
Accumulator Based Processor (Bangla)

English Version (Easy/Indian Style)Âļ

1. Important Registers to RememberÂļ

The Control Unit uses these registers to finish any task properly:
* Program Counter (PC): This box holds the address of the next instruction which the computer will run.
* Instruction Register (IR): This box holds the instruction which is running right now.
* Effective Address Register (EAR): This box keeps the address of the data we need to get from the memory.

2. How Computer Changes its PathÂļ

Normally, computer goes 1, 2, 3... in order. But in Figure 1.3, it shows two special cases:
alt text
* Branching (Jump): Look at picture 'a', the computer is at location 4, but suddenly it jumps to Location B. It skips the middle steps! 🔀
* Subroutine (Call): In picture 'b', at location 5, it calls a mini-program at location S. After finishing that work, it uses a Return instruction to come back to location 6. 🔄

📊 Quick Summary TableÂļ

Register Name What it does? Can you touch it?
PC Holds NEXT address ❌ No, it's dedicated!
IR Holds CURRENT work ❌ No, only for Control Unit!
EAR Holds DATA address ❌ No, it's private!

âš ī¸ Warning Emoji SectionÂļ

  • ❌ X Emoji: You cannot access these registers via your normal program because they are "Dedicated".
  • âš ī¸ Warning: If the Return instruction is missing in a Subroutine, the computer will get lost and won't know how to come back to the main program!

Boss, listen carefully. If we store everything in Solid-state memory, it will be very costly. That is why we use Secondary Memory like magnetic disks. It is a bit slow (turtle speed đŸĸ), but it can store huge files like your text editors or assemblers very cheaply.

To keep the computer fast, we use Memory-management algorithms. These algorithms "swap" data between primary and secondary memory in small pieces. So the CPU always finds its required item in the fast Primary memory.

đŸ› ī¸ Typical Data Values ExampleÂļ

Based on the text, let's see how values are handled:

Component Initial Value (Empty/Default) Provided Value (In Context)
RWM Word Size 0 bits 8-bit words
ROM Content Empty Unalterable info (e.g., Op-code table)
Secondary Memory Offline Huge Data Files/Programs

âŒ¨ī¸ I/O Devices & InterfaceÂļ

āχāωāϜāĻžāϰ āϟāĻžāĻ°ā§āĻŽāĻŋāύāĻžāϞ āĻŦāĻž āĻĒā§āϰāĻŋāĻ¨ā§āϟāĻžāϰ āĻĻāĻŋā§Ÿā§‡ āφāĻŽāϰāĻž āĻ•āĻŽā§āĻĒāĻŋāωāϟāĻžāϰ⧇āϰ āϏāĻžāĻĨ⧇ āĻ•āĻĨāĻž āĻŦāϞāĻŋāĨ¤ āĻ•āĻŋāĻ¨ā§āϤ⧁ āϏāĻŽāĻ¸ā§āϝāĻž āĻšāϞ⧋ CPU āϖ⧁āĻŦ āĻĢāĻžāĻ¸ā§āϟ āφāϰ āĻāχ āĻĄāĻŋāĻ­āĻžāχāϏāϗ⧁āϞ⧋ āĻ¸ā§āϞ⧋āĨ¤ āϤāĻžāχ āĻāĻĻ⧇āϰ āĻŽāĻ§ā§āϝ⧇ āĻ­āĻžāĻŦ āϜāĻŽāĻžāύ⧋āϰ āϜāĻ¨ā§āϝ Interface Circuitry āĻĒā§āĻ°ā§Ÿā§‹āϜāύ āĻšā§ŸāĨ¤

đŸ—ēī¸ Visualizing the Memory Evolution & FlowÂļ

Since you asked for timelines, here is a logical flow based on the tech mentioned

    graph TD
    subgraph "Year 1950s-1970s (Magnetic Era)"
    A[Magnetic Tapes/Disks] -->|Used as| B(Secondary Memory)
    end

    subgraph "Year 1980s-Present (Solid State Era)"
    C[IC Technology] -->|Creates| D(ROM & RWM)
    D -->|Organized as| E[8-bit Words]
    end

    B <-.->|Swapping via Algorithms| D
    D <--->|Direct Access| F[CPU]

    G[I/O Devices: Printer/Terminal] --- H{Interface Circuitry}
    H --- F

đŸšĢ Final Check of RulesÂļ

  • ❌ X Emoji: ROM-āĻāϰ āϭ⧇āϤāϰ⧇ āĻĨāĻžāĻ•āĻž 'Monitor Programs' āφāĻĒāύāĻŋ āϰāĻžāχāϟ āĻŦāĻž āĻĄāĻŋāϞāĻŋāϟ āĻ•āϰāϤ⧇ āĻĒāĻžāϰāĻŦ⧇āύ āύāĻžāĨ¤
  • âš ī¸ Warning: CPU āĻ•āĻ–āύ⧋āχ āϏāϰāĻžāϏāϰāĻŋ āϏ⧇āϕ⧇āĻ¨ā§āĻĄāĻžāϰāĻŋ āĻŽā§‡āĻŽā§‹āϰāĻŋāϰ āϏāĻžāĻĨ⧇ āĻ•āĻĨāĻž āĻŦāϞ⧇ āύāĻž, āϏāĻŦāϏāĻŽā§Ÿ āĻĒā§āϰāĻžāχāĻŽāĻžāϰāĻŋ āĻŽā§‡āĻŽā§‹āϰāĻŋ āĻšā§Ÿā§‡ āĻ•āĻžāϜ āĻ•āϰ⧇āĨ¤

1. Three Types of Busses (The Highway) đŸ›Ŗī¸Âļ

A Bus is just a set of wires to carry information.
* Address Bus: It is a "One-Way" street. CPU only sends address to Memory or I/O. If you have a 32-bit bus, you can find \(2^{32}\) (4 billion!) locations.
* Data Bus: It is a "Two-Way" street. Information goes from CPU to Memory and comes back also.
* Control Bus: It is like the "Traffic Signal". It tells everyone when to start or stop the I/O work.

2. Specialized Registers (The CPU's Pockets) đŸ—„ī¸Âļ

  • General Registers (\(R_0\) to \(R_7\)): Think of these as 8 small temporary pockets to store numbers or logic results.
  • Stack Pointer (SP): A special dedicated register that points to the top of the "Stack".
  • F Register (Flags): This is the "Status Report" box. If the last math result was zero, it sets the Z-flag to 1.

📊 Quick Sneak Peak: Operation Logic ExampleÂļ

Let's look at the ADD x, y, z instruction mentioned in image_4c7d03.jpg. This means: "Take value of x, add it to y, and store the result in z."

Register/Location Initial Value (Before ADD) Provided Value (After ADD x, y, z)
Location x 10 10 (Stays same)
Location y 20 20 (Stays same)
Location z 0 30 (New sum)
Z-Flag (in F) 0 0 (Since sum is not zero)

đŸ—ēī¸ Visualizing the Computer HierarchyÂļ

graph TD
    subgraph "System Bus Layer"
    A[Address Bus - Unidirectional] --> B[Memory/IO]
    C[Data Bus - Bidirectional] <--> B
    D[Control Bus - Signals] --> B
    end

    subgraph "CPU Organization Types"
    E[General Register]
    F[Accumulator]
    G[Stack Machine]
    end

    B --- E

đŸšĢ Common Pitfalls for BeginnersÂļ

  • ❌ Unidirectional vs Bidirectional: Never say Address bus is two-way. It is only one-way from the processor.
  • âš ī¸ The 32-bit Logic: If the bus size increases, the CPU can handle more memory. That's why modern computers are 64-bit!
  • ❌ Flags: Don't forget the F register. It tells the CPU if there was a math error or a zero result.