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12 Semester DiaryÂļ

232 Final Exam Routine

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13–14 NOV 2025

âš ī¸ āϜāϰ⧁āϰ⧀ āύ⧋āϟāĻŋāĻļâš ī¸
āĻĻ⧇āĻļ⧇āϰ āĻŦāĻ°ā§āϤāĻŽāĻžāύ āĻĒāϰāĻŋāĻ¸ā§āĻĨāĻŋāϤāĻŋāϰ āĻ•āĻžāϰāϪ⧇ āφāĻ—āĻžāĻŽā§€āĻ•āĻžāϞ 13.11.2025 āϤāĻžāϰāĻŋāϖ⧇ āĻ•ā§āϞāĻžāϏ āĻŦāĻ¨ā§āϧ āĻĨāĻžāĻ•āĻŦ⧇āĨ¤ āĻĒāϰāĻŦāĻ°ā§āϤ⧀ āĻĻāĻŋāύ⧇ āϝāĻĨāĻžāϰ⧀āϤāĻŋ āĻ•ā§āϞāĻžāϏ āϚāϞāĻŦ⧇āĨ¤
āϏāĻŦāĻžāχ āύāĻŋāϰāĻžāĻĒāĻĻ⧇ āĻĨāĻžāĻ•āĻŦ⧇āύāĨ¤


đŸŸĸ SPL Theory Assignment
Submission Date: 29-11-2025
Topic: Any topic from C program
Slides: 7-10 slides (PowerPoint)
Presentation Time: 5 minutes

Example of Assignment: Suppose you chose the topic "Array" from C. Now you have to write different types of codes and explanation or similar content related to Array at least 7 slides.

đŸŸĸ SPL Lab Assignment:
Please submit your Assignment (10 code slides given previously) to the Classroom.
https://classroom.google.com/u/1/c/ODIyMTg4MTk3MDcx
Google Classroom Code:dksbd6pb


12 Math Assignment 03.pdf

12 EEE Theory operational Amplifier.pdf

DLD Theory assignment 02:
Encoder,
1 Decoder - (3 to 8 decoder āύāĻŋāĻœā§‡āϰ function āĻĻāĻŋā§Ÿā§‡)
Multiplexer
PLA
ROM
DLD Theory Assignment
āϝāĻžāϰāĻž āĻāĻ–āύāĻ“ assignment 1 āĻĻ⧇āύāύāĻŋ āϤāĻžāϰāĻž āĻ…āĻŦāĻļā§āϝāχ āϏāĻžāĻŽāύ⧇āϰ āϏāĻĒā§āϤāĻžāĻš (⧍⧍ āύāϭ⧇.) āĻāϰ āĻŽāĻ§ā§āϝ⧇ āĻĻāĻŋāĻŦ⧇āύ, āĻāϰ āĻĒāϰ āĻ¸ā§āϝāĻžāϰ āφāϰ assignment 01 āϜāĻŽāĻž āύāĻŋāĻŦ⧇āύ āύāĻžāĨ¤
Assignment 02 Last Submission Date: 29-11-2025


Bangladesh Studies 08 Nov

07–08 NOV 2025

📘 Digital Logic Design Laboratory (DLD Lab)

đŸ§Ē Lab Examination
Date: 14 November 2025 (Friday)
Syllabus: All laboratory experiments except the Seven-Segment Display
Experiments to be covered:

All DLD Lab Lists:
āϏāĻŦāϗ⧁āϞ⧋ circuit solve āĻ•āϰ⧇ TinkerCad āĻ submit āĻ•āϰāϤ⧇ āĻšāĻŦ⧇āĨ¤
1.1: OR Gate
1.2: AND Gate
1.3: NOT Gate
3.1: NAND -> NOT, OR, AND āĻĻāĻŋā§Ÿā§‡
3.2: NOR -> NOT, OR, AND āĻĻāĻŋā§Ÿā§‡
3.3: NAND -> XNOR, XOR āĻĻāĻŋā§Ÿā§‡
3.3: NOR -> XNOR, XOR āĻĻāĻŋā§Ÿā§‡
4 (Circuit Design with K-Map solution )
4.1: Minterms: ∑M(1, 2, 4, 5, 7)
4.2: Minterms: ∑M(2,3,6,7,8,10,13,15)
4.3: Maxterms: ΠM(1, 2, 4, 5, 7)
4.4: Maxterms: ΠM(2,3,6,7,8,10,13,15)
5.1: Half Adder āĻĻāĻŋā§Ÿā§‡ circuit āĻ•āϰ⧇ TinkerCad āĻ submit āĻ•āϰāϤ⧇ āĻšāĻŦ⧇āĨ¤
5.2: Half Subtractor āĻĻāĻŋā§Ÿā§‡ circuit āĻ•āϰ⧇ TinkerCad āĻ submit āĻ•āϰāϤ⧇ āĻšāĻŦ⧇āĨ¤
6.1: Full Adder āĻĻāĻŋā§Ÿā§‡ circuit āĻ•āϰ⧇ TinkerCad āĻ submit āĻ•āϰāϤ⧇ āĻšāĻŦ⧇āĨ¤
6.2: Full Subtractor āĻĻāĻŋā§Ÿā§‡ circuit āĻ•āϰ⧇ TinkerCad āĻ submit āĻ•āϰāϤ⧇ āĻšāĻŦ⧇āĨ¤
7.1: 2-4 Decoder
7.2: 3-8 Decoder (Using two 2-4 decoder)
7.3: Encoder


âš™ī¸ Electronic Device and Circuits Laboratory (EEE 12P4)

📄 Assignment 02
Submission deadline: Mid-November 2025
Topic: NPN-type transistor and common-base configuration
Instructions:

  1. Draw and explain the circuit diagram of an npn-type BJT in common-base configuration.
  2. Define and discuss the input and output characteristics of a BJT.
  3. Plot the corresponding input and output characteristic curves.

📄 Assignment 03
Submission deadline: 29 November 2025
Topic: Analysis of BJT operation and active region
Instructions:

  1. Explain why a BJT does not conduct if the emitter–base junction is not forward-biased.
  2. Identify the active region from the output characteristics and explain with an example showing signal amplification.
  3. Illustrate the two-diode analogy of a BJT.

🧾 Laboratory Reports
All students must complete and prepare all EEE Laboratory Reports for submission within the department’s specified timeline.


💡 Electronic Device and Circuits Theory (EEE Theory)

📘 Assignment 02
Submission deadline: Mid-November 2025
Topic: Transistor configurations and performance comparison
Instructions:

  1. Discuss common-emitter and common-base configurations of an npn transistor.
  2. Explain transistor operation, current gain, and voltage gain. Include input resistance, output resistance, and the role of the load resistor in a common-emitter amplifier.
  3. Compare the characteristics of CB, CE, and CC configurations.

📏 Mathematics

📝 Assignment 02
Submission date: 14 November 2025

🧮 Class Test 02
Date: 14 November 2025


Bangladesh Studies

📖 Assignment 02
Topic: Bangladesh
Students must write concise analytical answers covering:
a. Historical Background
b. Geographical Importance
c. Society and Its Characteristics
d. Culture
e. Development Aspirations

Submission Deadline: Before the class test on 22 November 2025

📖 Assignment 03
Topic: Economy of Bangladesh
Focus on:

  • Major and Key Economic Sectors
  • Government Economic Strategies and Policies

Submission Deadline: Before the class test on 22 November 2025

🧾 Class Test
Date: 22 November 2025 (Saturday)

Syllabus: The class test will include both assignment topics and selected historical and political events.

Included Chapters:

  1. Bangladesh (Assignments 02 and 03)

  2. Historical Background

  3. Geographical Importance
  4. Society and Culture
  5. Development Aspirations
  6. Economy: Key Sectors and Government Strategy
  7. The First Independence Movement of India (1857)
  8. The Political Partition of India
  9. Bongobhongo (Partition of Bengal, 1905)
  10. The Partition of 1947
17-18 OCT 2025

đŸŸĸ EEE Theory:
⭐ āφāĻ—āĻžāĻŽā§€ āĻ•ā§āϞāĻžāϏ⧇ āĻĒāϰ⧀āĻ•ā§āώāĻžāĨ¤ ⧍ āϟāĻž āĻĒā§āϰāĻļā§āύ āĻĨāĻžāĻ•āĻŦ⧇āσ
ā§§āĻŽ āĻĒā§āϰāĻļā§āύ⧇āϰ topics: (Norton's Theorem, Thevenin's Theorem, Maximum Power Transfer Theorem)
⧍⧟ āĻĒā§āϰāĻļā§āύ⧇āϰ topics: Diode āĻĨ⧇āϕ⧇ - (Half Wave Rectifier, Full Wave Rectifier, Bridge Rectifier, Ripple Factor )
āĻĒā§āϰāϤāĻŋāϟāĻžāϰāχ Equation + Math related āĻĒā§āϰāĻļā§āύ āĻĨāĻžāĻ•āĻŦ⧇āĨ¤

đŸŸĸ Math
Linear Algebra āĻĨ⧇āϕ⧇ āĻļ⧇āώ āĻ•ā§Ÿā§‡āĻ•āϟāĻž math āĻ•āϰāĻžāύ⧋ āĻšā§Ÿā§‡āϛ⧇ āĻāĻŦāĻ‚ Matrix basic āφāϞ⧋āϚāύāĻž āĻ•āϰāĻž āĻšā§Ÿā§‡āϛ⧇āĨ¤ āύ⧋āϟ āĻĻā§‡ā§ŸāĻž āĻšā§Ÿā§‡āϛ⧇āĨ¤

đŸŸĸ DLD Lab:
7.1: 2-4 Decoder
7.2: 3-8 Decoder (Using two 2-4 decoder)
āĻāϟāĻž āφāĻ—āĻžāĻŽā§€ āϏāĻĒā§āϤāĻžāĻšā§‡āϰ āϜāĻ¨ā§āϝāσ 7.3: Encoder

đŸŸĸ EEE Lab:
Lab 05: Determination of Bipolar Junction Transistor (BJT) Characteristics
https://drive.google.com/file/d/1WhcfwJOveMRmxDER7VTCHg8-jEBgNvog/view?usp=drive_link

đŸŸĸ SPL Theory:
For Loop āĻĻāĻŋā§Ÿā§‡ āϗ⧁āϪ⧇āϰ āύāĻžāĻŽāϤāĻžāĨ¤

đŸŸĸ DLD Theory:
Encoder, Multiplexer, 2-1 MUX, 8-1 MUX, 4-1 MUX,
1. Implementation of a 4 input multiplexer using only 2-input multiplexer,
2. Design a combinational circuit to implement a 4-bit Full adder-subtractor u sing Full adder and multiplexer
3. Design a combinational circuit that accept 3-inputs and generates an output binary number equal to the input number plus one output.

đŸŸĸBangladesh Studies:
āĻŦā§āϰāĻŋāϟāĻŋāĻļ āĻļāĻžāϏāύ āĻļ⧁āϰ⧁ āĻĨ⧇āϕ⧇ āĻļ⧇āώ āĻ•āϰāĻžāϰ āĻ•āĻŋāϛ⧁āϟāĻž āĻŦāĻžāϕ⧀āĨ¤

đŸŸĸ SPL Lab
Loop use āĻ•āϰ⧇:
Number righ-angle-triangle,
Number reversed righ-angle-triangle,
Reversed righ-angle-triangle showing asterisk (*),
SPL Lab patterns

OCT 10-11 2025

đŸŸĸ āĻ āϏāĻĒā§āϤāĻžāĻšā§‡ āĻāĻ•ā§āϏāĻžāĻŽ āĻšā§Ÿā§‡āϛ⧇āĨ¤ āφāĻ—āĻžāĻŽā§€ āϏāĻĒā§āϤāĻžāĻšā§‡ (18 OCT 2025) āφāĻŦāĻžāϰāĻ“ āĻāĻ•ā§āϏāĻžāĻŽ āĻ¨ā§‡ā§ŸāĻž āĻšāĻŦ⧇ SPL Lab āĻāϰāĨ¤ āϏāĻŋāϞ⧇āĻŦāĻžāϏ āφāϗ⧇āϰ āϗ⧁āϞ⧋āχāĨ¤

đŸŸĸ āϝāĻžāϰāĻž DLD Theory Assignment āϜāĻŽāĻž āĻĻ⧇āύāύāĻŋ āĻĻāĻŋā§Ÿā§‡ āĻĻ⧇āĻŦ⧇āύāĨ¤

đŸŸĸ āĻ āϏāĻĒā§āϤāĻžāĻšā§‡ Math assignment - 02 āĻĻā§‡ā§Ÿ āĻšā§Ÿā§‡āϛ⧇āĨ¤ āĻļ⧇āώ āϤāĻžāϰāĻŋāĻ– āĻĒāϰ⧇ āϜāĻžāύāĻŋā§Ÿā§‡ āĻĻā§‡ā§ŸāĻž āĻšāĻŦ⧇āĨ¤
12 Math Assignment 02 232 term

đŸŸĸ Bangladesh Studies āĻ¸ā§āϝāĻžāϰ āĻāχ week āĻ āφāϏ⧇āύāύāĻŋāĨ¤ āϝāĻžāϰāĻž assignment āĻĻ⧇āύāύāĻŋ, āύ⧇āĻ•ā§āϏāϟ āϏāĻĒā§āϤāĻžāĻš āĻĒāĻ°ā§āϝāĻ¨ā§āϤ āϜāĻŽāĻž āĻĻāĻŋāϤ⧇ āĻĒāĻžāϰāĻŦ⧇āύāĨ¤

đŸŸĸ DLD Lab:
✅ 6.1: Full Adder āĻĻāĻŋā§Ÿā§‡ circuit āĻ•āϰ⧇ TinkerCad āĻ submit āĻ•āϰāϤ⧇ āĻšāĻŦ⧇āĨ¤
✅ 6.2: Full Subtractor āĻĻāĻŋā§Ÿā§‡ circuit āĻ•āϰ⧇ TinkerCad āĻ submit āĻ•āϰāϤ⧇ āĻšāĻŦ⧇āĨ¤

āϏāĻ•āϞ āĻĢāĻžāχāϞ āĻĒ⧇āϤ⧇ āĻāχ āĻĢā§‹āĻ˛ā§āĻĄāĻžāϰ āĻšā§‡āĻ• āĻ•āϰ⧁āύāσ

20 SEPT 2025
  • DLD Lab:Âļ

    ✅ 5.1: Half Adder āĻĻāĻŋā§Ÿā§‡ circuit āĻ•āϰ⧇ TinkerCad āĻ submit āĻ•āϰāϤ⧇ āĻšāĻŦ⧇āĨ¤
    ✅ 5.2: Half Subtractor āĻĻāĻŋā§Ÿā§‡ circuit āĻ•āϰ⧇ TinkerCad āĻ submit āĻ•āϰāϤ⧇ āĻšāĻŦ⧇āĨ¤

  • DLD Theory:Âļ

    Lecture: Design of a conditional Circuit, āĻāĻ–āĻžāύ⧇ Truth Table, KMap āĻĻāĻŋā§Ÿā§‡ 2 āϟāĻž math āĻ•āϰāĻžāύ⧋ āĻšā§Ÿā§‡āϛ⧇ circuit āϏāĻšāĨ¤

    • HW: Digital watch āĻāϰ 0-9 digits āϗ⧁āϞ⧋āϰ āϜāĻ¨ā§āϝ circuit āĻāϕ⧇ āϤāĻž simulate āĻ•āϰāϤ⧇ āĻšāĻŦ⧇āĨ¤
    • āϝāĻžāϰāĻž DLD theory assignment āϜāĻŽāĻž āĻāĻ–āύāĻ“ āĻĻ⧇āύāύāĻŋ, āφāĻ—āĻžāĻŽā§€ āϏāĻĒā§āϤāĻžāĻšā§‡āϰ āĻŽāĻ§ā§āϝ⧇āχ āĻĻāĻŋā§Ÿā§‡ āĻĻāĻŋāĻŦ⧇āύāĨ¤
  • EEE Lab:Âļ

    āĻ¸ā§āϝāĻžāϰ āφāϏ⧇āύāύāĻŋ āĻ•ā§āϞāĻžāϏ āĻšā§ŸāύāĻŋāĨ¤ Robin āĻ­āĻžāχ āĻāϏ⧇ rectifier āĻĻāĻŋā§Ÿā§‡ experiment āĻ•āϰāĻžāϰ āĻšā§‡āĻˇā§āϟāĻž āĻ•āϰ⧇āϛ⧇āύ, āϝāĻžāĻ¨ā§āĻ¤ā§āϰāĻŋāĻ• āĻ¤ā§āϰ⧁āϟāĻŋāϰ āĻ•āĻžāϰāϪ⧇ āϏ⧇āϟāĻžāĻ“ āĻ āĻŋāĻ•āĻ āĻžāĻ• āĻšā§ŸāύāĻŋāĨ¤
    EEE Lab Exam: āϏāĻŦāĻžāχāϕ⧇ āĻŦāϞāĻŦ⧇āύ āϏāĻžāĻŽāύ⧇āϰ āĻ•ā§āϞāĻžāϏ⧇ āĻ˛ā§āϝāĻžāĻŦ āĻĒāϰ⧀āĻ•ā§āώāĻž āĻšāĻŦ⧇ āĻāĻŦāĻ‚ full wave rectifier āĻ­āĻžāϞ āĻ•āϰ⧇ āĻĒ⧜āĻžāĻļ⧁āύāĻž āĻ•āϰ⧇ āφāϏāĻŦ⧇āύ āĻāĻŦāĻ‚ youtube āĻ oscilloscope āĻŦā§āϝāĻžāĻŦāĻšāĻžāϰ āĻŦāĻŋāϧāĻŋ āĻ­āĻžāϞ āĻ•āϰ⧇ āĻļāĻŋāϖ⧇ āφāϏāĻŦ⧇āύāĨ¤

  • EEE Theory:Âļ

    • Zener diode, PNP and NPN Junction, Emitter, Collector, Base.
    • Assignment Reminder: āϝāĻžāϰāĻž āĻāĻ–āύāĻ“ āφāϗ⧇āϰ assignment āĻĻ⧇āύāύāĻŋ āϤāĻžāϰāĻž āĻĻāĻŋā§Ÿā§‡ āĻĻāĻŋāĻŦ⧇āύāĨ¤
  • Bangladesh Studies:Âļ

    Subject: Assignment SubmissionÂļ

    Topic: The Ancient Trade of India with Rome
    Length: 2000 – 2500 words
    Date: 20th September
    Deadline: 26th September

    Assignment instructions:Âļ

    1. Introduction (āĻ­ā§‚āĻŽāĻŋāĻ•āĻž)
    2. Topic-āĻāϰ āϏāĻ‚āĻ•ā§āώāĻŋāĻĒā§āϤ āĻĒāϰāĻŋāϚ⧟ āĻ“ āϗ⧁āϰ⧁āĻ¤ā§āĻŦ
    3. Historical Background (āϐāϤāĻŋāĻšāĻžāϏāĻŋāĻ• āĻĒā§āϰ⧇āĻ•ā§āώāĻžāĻĒāϟ)
    4. Political context of India and Rome
    5. āϏāĻŽāϏāĻžāĻŽā§ŸāĻŋāĻ• āϰāĻžāϜāύ⧀āϤāĻŋ, āĻļāĻžāϏāύ āĻŦā§āϝāĻŦāĻ¸ā§āĻĨāĻž āĻ“ āϐāϤāĻŋāĻšāĻžāϏāĻŋāĻ• āϘāϟāύāĻž
    6. Ancient Trade (āĻĒā§āϰāĻžāĻšā§€āύ āĻŦāĻžāĻŖāĻŋāĻœā§āϝ āϏāĻŽā§āĻĒāĻ°ā§āĻ•)
    7. Nature of trade (land route & sea route)
    8. āĻĒā§āϰāϧāĻžāύ āĻŦāĻžāĻŖāĻŋāĻœā§āϝ āϕ⧇āĻ¨ā§āĻĻā§āϰ āĻ“ āĻŦāĻ¨ā§āĻĻāϰ
    9. Trade theories and historical evidence
    10. Economical Context (āĻ…āĻ°ā§āĻĨāύ⧈āϤāĻŋāĻ• āĻĒā§āϰ⧇āĻ•ā§āώāĻžāĻĒāϟ)
    11. Indo-Roman trade āĻāϰ āĻ…āĻ°ā§āĻĨāύ⧈āϤāĻŋāĻ• āĻĒā§āϰāĻ­āĻžāĻŦ
    12. Import–Export Analysis (āφāĻŽāĻĻāĻžāύāĻŋ–āϰāĻĒā§āϤāĻžāύāĻŋ āĻŦāĻŋāĻļā§āϞ⧇āώāĻŖ)
    13. Exports from India → Spices, textiles, pearls, ivory, silk
    14. Imports from Rome → Wine, coral, olive oil, luxury items
    15. Balance of trade discussion
    16. Conclusion (āωāĻĒāϏāĻ‚āĻšāĻžāϰ)
      Note: āĻšāĻžāϤ⧇ āϞāĻŋāĻ–āϤ⧇ āĻšāĻŦ⧇āĨ¤

    Bangladesh Studies Exam

    Exam Topics (Short Questions):
    1. History – Necessity of History
    2. State – Characteristics of Modern State
    3. Pal Era
    4. Sen Era
    5. Context of Muslim Expedition in India
    6. Independent Sultanate of Bengal
    7. Expedition of Bengal by Bakhtiar Khilji

    📌 Note:
    * āĻĒāϰ⧀āĻ•ā§āώāĻžā§Ÿ āĻļ⧁āϧ⧁āĻŽāĻžāĻ¤ā§āϰ āĻ…āĻ˛ā§āĻĒ āύāĻŽā§āĻŦāϰ⧇āϰ Short Questions āĻĨāĻžāĻ•āĻŦ⧇āĨ¤
    * āωāĻĒāϰ⧋āĻ•ā§āϤ āĻŦāĻŋāώ⧟āϗ⧁āϞ⧋ āĻĨ⧇āϕ⧇ āĻĒā§āϰāĻļā§āύ āĻ•āϰāĻž āĻšāĻŦ⧇āĨ¤

26-27 SEPT 2025

🔴āφāĻ—āĻžāĻŽā§€ ā§§ā§§āϤāĻžāϰāĻŋāĻ– SPL Exam āĻšāĻŦ⧇āĨ¤
Exam Topic:āĻļ⧁āϰ⧁ āĻĨ⧇āϕ⧇ Loop āĻĒāĻ°ā§āϝāĻ¨ā§āϤ āĻ¸ā§āϝāĻžāϰ āϝāĻž āĻĒ⧜āĻŋā§Ÿā§‡āϛ⧇āύāĨ¤

🔴SPL Theory Assignment:
āĻ¸ā§āϝāĻžāϰ āĻāχ āĻĒāĻ°ā§āϝāĻ¨ā§āϤ āϝāĻž āĻĒ⧜āĻŋā§Ÿā§‡āϛ⧇āύ āϤāĻžāϰ āĻŽāĻ§ā§āϝ⧇ āĻĨ⧇āϕ⧇ ā§§ā§ĻāϟāĻž Question āύāĻŋāĻœā§‡āϰ āĻŽāϤ⧋ āĻ•āϰ⧇ āĻŦāĻžāύāĻŋā§Ÿā§‡ āϏ⧇āϗ⧁āϞ⧋āϰ Answer āϤ⧈āϰāĻŋ āĻ•āϰāϤ⧇ āĻšāĻŦ⧇āĨ¤
Deadline:11 October

🔴SPL Lab Assignment:
āĻāχ āĻĒāĻ°ā§āϝāĻ¨ā§āϤ āϝāϤ āϟāĻĒāĻŋāϕ⧇āϰ āωāĻĒāϰ āĻ˛ā§āϝāĻžāĻŦ āĻšā§Ÿā§‡āϛ⧇ āϤāĻžāϰ āĻŽāĻ§ā§āϝ āĻĨ⧇āϕ⧇ ā§§ā§ĻāϟāĻž āĻĒā§āϰ⧋āĻ—ā§āϰāĻžāĻŽ āĻŦāĻžāύāĻŋā§Ÿā§‡ PowerPoint āĻ āĻĒ⧇āĻ¸ā§āϟ āĻ•āϰāϤ⧇ āĻšāĻŦ⧇āĨ¤āϝ⧇ āĻĒā§āϰ⧋āĻ—ā§āϰāĻžāĻŽ āĻ•āϰ⧇āϛ⧇āύ āϏ⧇āĻ–āĻžāύ⧇ āϝāĻž āĻ•āĻŋāϛ⧁ āχāωāϜ āĻ•āϰ⧇āϛ⧇āύ āϤāĻžāϰ āϏāĻŽā§āĻĒāĻ°ā§āϕ⧇ āϞāĻŋāĻ–āĻŦ⧇āύ(āϝ⧇āĻŽāύ: āĻāĻ•āϟāĻž āĻĒā§āϰ⧋āĻ—ā§āϰāĻžāĻŽ āĻ āχāωāϜ āĻ•āϰ⧇āϛ⧇āύ for loop. āĻĒā§āϰ⧋āĻ—ā§āϰāĻžāĻŽ āĻāϰ āύāĻŋāĻšā§‡ for loop āĻ•āĻŋ āϕ⧇āύ⧋ āχāωāϏ āĻ•āϰāϤ⧇ āĻšā§ŸāĨ¤ āĻāĻ›āĻžā§œāĻž int, main āϝāĻžāĻ•āĻŋāϛ⧁ āĻĒā§āϰ⧋āĻ—ā§āϰāĻžāĻŽ āĻ āχāωāϜ āĻ•āϰāĻŦ⧇āύ āϤāĻžāϰ āϏāĻŽā§āĻĒāĻ°ā§āϕ⧇ āϞāĻŋāĻ–āĻŦ⧇āύ)āĨ¤ Presentation āĻāϰ āĻŽāϤ⧋ āĻ•āϰ⧇ āĻ•āϰāϤ⧇ āĻšāĻŦ⧇āĨ¤
Deadline:11 October.

đŸ”´ā§§ā§§ āϤāĻžāϰāĻŋāĻ– SPL Lab āĻāĻ•ā§āϏāĻžāĻŽ āĻšāĻŦ⧇āĨ¤
Lab Exam Topic:āĻļ⧁āϰ⧁ āĻĨ⧇āϕ⧇ Loop āĻĒāĻ°ā§āϝāĻ¨ā§āϤ āϝāϤ āϟāĻĒāĻŋāϕ⧇āϰ āωāĻĒāϰ āĻ˛ā§āϝāĻžāĻŦ āĻ•ā§āϞāĻžāϏ āĻšā§Ÿā§‡āϛ⧇āĨ¤


All DLD Lab Lists:

āϏāĻŦāϗ⧁āϞ⧋ circuit solve āĻ•āϰ⧇ TinkerCad āĻ submit āĻ•āϰāϤ⧇ āĻšāĻŦ⧇āĨ¤
1.1: OR Gate
1.2: AND Gate
1.3: NOT Gate
3.1: NAND -> NOT, OR, AND āĻĻāĻŋā§Ÿā§‡
3.2: NOR -> NOT, OR, AND āĻĻāĻŋā§Ÿā§‡
3.3: NAND -> XNOR, XOR āĻĻāĻŋā§Ÿā§‡
3.3: NOR -> XNOR, XOR āĻĻāĻŋā§Ÿā§‡
4 (Circuit Design with K-Map solution )
4.1: Minterms: ∑M(1, 2, 4, 5, 7)
4.2: Minterms: ∑M(2,3,6,7,8,10,13,15)
4.3: Maxterms: ΠM(1, 2, 4, 5, 7)
4.4: Maxterms: ΠM(2,3,6,7,8,10,13,15)
5.1: Half Adder āĻĻāĻŋā§Ÿā§‡ circuit āĻ•āϰ⧇ TinkerCad āĻ submit āĻ•āϰāϤ⧇ āĻšāĻŦ⧇āĨ¤
5.2: Half Subtractor āĻĻāĻŋā§Ÿā§‡ circuit āĻ•āϰ⧇ TinkerCad āĻ submit āĻ•āϰāϤ⧇ āĻšāĻŦ⧇āĨ¤
6.1: Full Adder āĻĻāĻŋā§Ÿā§‡ circuit āĻ•āϰ⧇ TinkerCad āĻ submit āĻ•āϰāϤ⧇ āĻšāĻŦ⧇āĨ¤
6.2: Full Subtractor āĻĻāĻŋā§Ÿā§‡ circuit āĻ•āϰ⧇ TinkerCad āĻ submit āĻ•āϰāϤ⧇ āĻšāĻŦ⧇āĨ¤
7.1: 2-4 Decoder
7.2: 3-8 Decoder (Using two 2-4 decoder)
7.3: Encoder