12 Semester DiaryÂļ
13â14 NOV 2025
â ī¸ āĻāϰā§āϰ⧠āύā§āĻāĻŋāĻļâ ī¸
āĻĻā§āĻļā§āϰ āĻŦāϰā§āϤāĻŽāĻžāύ āĻĒāϰāĻŋāϏā§āĻĨāĻŋāϤāĻŋāϰ āĻāĻžāϰāĻŖā§ āĻāĻāĻžāĻŽā§āĻāĻžāϞ 13.11.2025 āϤāĻžāϰāĻŋāĻā§ āĻā§āϞāĻžāϏ āĻŦāύā§āϧ āĻĨāĻžāĻāĻŦā§āĨ¤ āĻĒāϰāĻŦāϰā§āϤ⧠āĻĻāĻŋāύ⧠āϝāĻĨāĻžāϰā§āϤāĻŋ āĻā§āϞāĻžāϏ āĻāϞāĻŦā§āĨ¤
āϏāĻŦāĻžāĻ āύāĻŋāϰāĻžāĻĒāĻĻā§ āĻĨāĻžāĻāĻŦā§āύāĨ¤
đĸ SPL Theory Assignment
Submission Date: 29-11-2025
Topic: Any topic from C program
Slides: 7-10 slides (PowerPoint)
Presentation Time: 5 minutes
Example of Assignment: Suppose you chose the topic "Array" from C. Now you have to write different types of codes and explanation or similar content related to Array at least 7 slides.
đĸ SPL Lab Assignment:
Please submit your Assignment (10 code slides given previously) to the Classroom.
https://classroom.google.com/u/1/c/ODIyMTg4MTk3MDcx
Google Classroom Code:dksbd6pb
12 EEE Theory operational Amplifier.pdf
DLD Theory assignment 02:
Encoder,
1 Decoder - (3 to 8 decoder āύāĻŋāĻā§āϰ function āĻĻāĻŋā§ā§)
Multiplexer
PLA
ROM
DLD Theory Assignment
āϝāĻžāϰāĻž āĻāĻāύāĻ assignment 1 āĻĻā§āύāύāĻŋ āϤāĻžāϰāĻž āĻ
āĻŦāĻļā§āϝāĻ āϏāĻžāĻŽāύā§āϰ āϏāĻĒā§āϤāĻžāĻš (⧍⧍ āύāĻā§.) āĻāϰ āĻŽāϧā§āϝ⧠āĻĻāĻŋāĻŦā§āύ, āĻāϰ āĻĒāϰ āϏā§āϝāĻžāϰ āĻāϰ assignment 01 āĻāĻŽāĻž āύāĻŋāĻŦā§āύ āύāĻžāĨ¤
Assignment 02 Last Submission Date: 29-11-2025
07â08 NOV 2025
đ Digital Logic Design Laboratory (DLD Lab)
đ§Ē Lab Examination
Date: 14 November 2025 (Friday)
Syllabus: All laboratory experiments except the Seven-Segment Display
Experiments to be covered:
All DLD Lab Lists:
āϏāĻŦāĻā§āϞ⧠circuit solve āĻāϰ⧠TinkerCad āĻ submit āĻāϰāϤ⧠āĻšāĻŦā§āĨ¤
1.1: OR Gate
1.2: AND Gate
1.3: NOT Gate
3.1: NAND -> NOT, OR, AND āĻĻāĻŋā§ā§
3.2: NOR -> NOT, OR, AND āĻĻāĻŋā§ā§
3.3: NAND -> XNOR, XOR āĻĻāĻŋā§ā§
3.3: NOR -> XNOR, XOR āĻĻāĻŋā§ā§
4 (Circuit Design with K-Map solution )
4.1: Minterms: âM(1, 2, 4, 5, 7)
4.2: Minterms: âM(2,3,6,7,8,10,13,15)
4.3: Maxterms: Î M(1, 2, 4, 5, 7)
4.4: Maxterms: Î M(2,3,6,7,8,10,13,15)
5.1: Half Adder āĻĻāĻŋā§ā§ circuit āĻāϰ⧠TinkerCad āĻ submit āĻāϰāϤ⧠āĻšāĻŦā§āĨ¤
5.2: Half Subtractor āĻĻāĻŋā§ā§ circuit āĻāϰ⧠TinkerCad āĻ submit āĻāϰāϤ⧠āĻšāĻŦā§āĨ¤
6.1: Full Adder āĻĻāĻŋā§ā§ circuit āĻāϰ⧠TinkerCad āĻ submit āĻāϰāϤ⧠āĻšāĻŦā§āĨ¤
6.2: Full Subtractor āĻĻāĻŋā§ā§ circuit āĻāϰ⧠TinkerCad āĻ submit āĻāϰāϤ⧠āĻšāĻŦā§āĨ¤
7.1: 2-4 Decoder
7.2: 3-8 Decoder (Using two 2-4 decoder)
7.3: Encoder
âī¸ Electronic Device and Circuits Laboratory (EEE 12P4)
đ Assignment 02
Submission deadline: Mid-November 2025
Topic: NPN-type transistor and common-base configuration
Instructions:
- Draw and explain the circuit diagram of an npn-type BJT in common-base configuration.
- Define and discuss the input and output characteristics of a BJT.
- Plot the corresponding input and output characteristic curves.
đ Assignment 03
Submission deadline: 29 November 2025
Topic: Analysis of BJT operation and active region
Instructions:
- Explain why a BJT does not conduct if the emitterâbase junction is not forward-biased.
- Identify the active region from the output characteristics and explain with an example showing signal amplification.
- Illustrate the two-diode analogy of a BJT.
đ§ž Laboratory Reports
All students must complete and prepare all EEE Laboratory Reports for submission within the departmentâs specified timeline.
đĄ Electronic Device and Circuits Theory (EEE Theory)
đ Assignment 02
Submission deadline: Mid-November 2025
Topic: Transistor configurations and performance comparison
Instructions:
- Discuss common-emitter and common-base configurations of an npn transistor.
- Explain transistor operation, current gain, and voltage gain. Include input resistance, output resistance, and the role of the load resistor in a common-emitter amplifier.
- Compare the characteristics of CB, CE, and CC configurations.
đ Mathematics
đ Assignment 02
Submission date: 14 November 2025
đ§Ž Class Test 02
Date: 14 November 2025
Bangladesh Studies
đ Assignment 02
Topic: Bangladesh
Students must write concise analytical answers covering:
a. Historical Background
b. Geographical Importance
c. Society and Its Characteristics
d. Culture
e. Development Aspirations
Submission Deadline: Before the class test on 22 November 2025
đ Assignment 03
Topic: Economy of Bangladesh
Focus on:
- Major and Key Economic Sectors
- Government Economic Strategies and Policies
Submission Deadline: Before the class test on 22 November 2025
đ§ž Class Test
Date: 22 November 2025 (Saturday)
Syllabus: The class test will include both assignment topics and selected historical and political events.
Included Chapters:
-
Bangladesh (Assignments 02 and 03)
-
Historical Background
- Geographical Importance
- Society and Culture
- Development Aspirations
- Economy: Key Sectors and Government Strategy
- The First Independence Movement of India (1857)
- The Political Partition of India
- Bongobhongo (Partition of Bengal, 1905)
- The Partition of 1947
17-18 OCT 2025
đĸ EEE Theory:
â āĻāĻāĻžāĻŽā§ āĻā§āϞāĻžāϏ⧠āĻĒāϰā§āĻā§āώāĻžāĨ¤ ⧍ āĻāĻž āĻĒā§āϰāĻļā§āύ āĻĨāĻžāĻāĻŦā§āĻ
ā§§āĻŽ āĻĒā§āϰāĻļā§āύā§āϰ topics: (Norton's Theorem, Thevenin's Theorem, Maximum Power Transfer Theorem)
⧍⧠āĻĒā§āϰāĻļā§āύā§āϰ topics: Diode āĻĨā§āĻā§ - (Half Wave Rectifier, Full Wave Rectifier, Bridge Rectifier, Ripple Factor )
āĻĒā§āϰāϤāĻŋāĻāĻžāϰāĻ Equation + Math related āĻĒā§āϰāĻļā§āύ āĻĨāĻžāĻāĻŦā§āĨ¤
đĸ Math
Linear Algebra āĻĨā§āĻā§ āĻļā§āώ āĻā§ā§āĻāĻāĻž math āĻāϰāĻžāύ⧠āĻšā§ā§āĻā§ āĻāĻŦāĻ Matrix basic āĻāϞā§āĻāύāĻž āĻāϰāĻž āĻšā§ā§āĻā§āĨ¤ āύā§āĻ āĻĻā§ā§āĻž āĻšā§ā§āĻā§āĨ¤
đĸ DLD Lab:
7.1: 2-4 Decoder
7.2: 3-8 Decoder (Using two 2-4 decoder)
āĻāĻāĻž āĻāĻāĻžāĻŽā§ āϏāĻĒā§āϤāĻžāĻšā§āϰ āĻāύā§āϝāĻ 7.3: Encoder
đĸ EEE Lab:
Lab 05: Determination of Bipolar Junction Transistor (BJT) Characteristics
https://drive.google.com/file/d/1WhcfwJOveMRmxDER7VTCHg8-jEBgNvog/view?usp=drive_link
đĸ SPL Theory:
For Loop āĻĻāĻŋā§ā§ āĻā§āĻŖā§āϰ āύāĻžāĻŽāϤāĻžāĨ¤
đĸ DLD Theory:
Encoder, Multiplexer, 2-1 MUX, 8-1 MUX, 4-1 MUX,
1. Implementation of a 4 input multiplexer using only 2-input multiplexer,
2. Design a combinational circuit to implement a 4-bit Full adder-subtractor u sing Full adder and multiplexer
3. Design a combinational circuit that accept 3-inputs and generates an output binary number equal to the input number plus one output.
đĸBangladesh Studies:
āĻŦā§āϰāĻŋāĻāĻŋāĻļ āĻļāĻžāϏāύ āĻļā§āϰ⧠āĻĨā§āĻā§ āĻļā§āώ āĻāϰāĻžāϰ āĻāĻŋāĻā§āĻāĻž āĻŦāĻžāĻā§āĨ¤
đĸ SPL Lab
Loop use āĻāϰā§:
Number righ-angle-triangle,
Number reversed righ-angle-triangle,
Reversed righ-angle-triangle showing asterisk (*),

OCT 10-11 2025
đĸ āĻ āϏāĻĒā§āϤāĻžāĻšā§ āĻāĻā§āϏāĻžāĻŽ āĻšā§ā§āĻā§āĨ¤ āĻāĻāĻžāĻŽā§ āϏāĻĒā§āϤāĻžāĻšā§ (18 OCT 2025) āĻāĻŦāĻžāϰāĻ āĻāĻā§āϏāĻžāĻŽ āύā§ā§āĻž āĻšāĻŦā§ SPL Lab āĻāϰāĨ¤ āϏāĻŋāϞā§āĻŦāĻžāϏ āĻāĻā§āϰ āĻā§āϞā§āĻāĨ¤
đĸ āϝāĻžāϰāĻž DLD Theory Assignment āĻāĻŽāĻž āĻĻā§āύāύāĻŋ āĻĻāĻŋā§ā§ āĻĻā§āĻŦā§āύāĨ¤
đĸ āĻ āϏāĻĒā§āϤāĻžāĻšā§ Math assignment - 02 āĻĻā§ā§ āĻšā§ā§āĻā§āĨ¤ āĻļā§āώ āϤāĻžāϰāĻŋāĻ āĻĒāϰ⧠āĻāĻžāύāĻŋā§ā§ āĻĻā§ā§āĻž āĻšāĻŦā§āĨ¤
12 Math Assignment 02 232 term
đĸ Bangladesh Studies āϏā§āϝāĻžāϰ āĻāĻ week āĻ āĻāϏā§āύāύāĻŋāĨ¤ āϝāĻžāϰāĻž assignment āĻĻā§āύāύāĻŋ, āύā§āĻā§āϏāĻ āϏāĻĒā§āϤāĻžāĻš āĻĒāϰā§āϝāύā§āϤ āĻāĻŽāĻž āĻĻāĻŋāϤ⧠āĻĒāĻžāϰāĻŦā§āύāĨ¤
đĸ DLD Lab:
â
6.1: Full Adder āĻĻāĻŋā§ā§ circuit āĻāϰ⧠TinkerCad āĻ submit āĻāϰāϤ⧠āĻšāĻŦā§āĨ¤
â
6.2: Full Subtractor āĻĻāĻŋā§ā§ circuit āĻāϰ⧠TinkerCad āĻ submit āĻāϰāϤ⧠āĻšāĻŦā§āĨ¤
āϏāĻāϞ āĻĢāĻžāĻāϞ āĻĒā§āϤ⧠āĻāĻ āĻĢā§āϞā§āĻĄāĻžāϰ āĻā§āĻ āĻāϰā§āύāĻ
20 SEPT 2025
-
DLD Lab:Âļ
â 5.1: Half Adder āĻĻāĻŋā§ā§ circuit āĻāϰ⧠TinkerCad āĻ submit āĻāϰāϤ⧠āĻšāĻŦā§āĨ¤
â 5.2: Half Subtractor āĻĻāĻŋā§ā§ circuit āĻāϰ⧠TinkerCad āĻ submit āĻāϰāϤ⧠āĻšāĻŦā§āĨ¤ -
DLD Theory:Âļ
Lecture: Design of a conditional Circuit, āĻāĻāĻžāύ⧠Truth Table, KMap āĻĻāĻŋā§ā§ 2 āĻāĻž math āĻāϰāĻžāύ⧠āĻšā§ā§āĻā§ circuit āϏāĻšāĨ¤
- HW: Digital watch āĻāϰ 0-9 digits āĻā§āϞā§āϰ āĻāύā§āϝ circuit āĻāĻā§ āϤāĻž simulate āĻāϰāϤ⧠āĻšāĻŦā§āĨ¤
- āϝāĻžāϰāĻž DLD theory assignment āĻāĻŽāĻž āĻāĻāύāĻ āĻĻā§āύāύāĻŋ, āĻāĻāĻžāĻŽā§ āϏāĻĒā§āϤāĻžāĻšā§āϰ āĻŽāϧā§āϝā§āĻ āĻĻāĻŋā§ā§ āĻĻāĻŋāĻŦā§āύāĨ¤
-
EEE Lab:Âļ
āϏā§āϝāĻžāϰ āĻāϏā§āύāύāĻŋ āĻā§āϞāĻžāϏ āĻšā§āύāĻŋāĨ¤ Robin āĻāĻžāĻ āĻāϏ⧠rectifier āĻĻāĻŋā§ā§ experiment āĻāϰāĻžāϰ āĻā§āώā§āĻāĻž āĻāϰā§āĻā§āύ, āϝāĻžāύā§āϤā§āϰāĻŋāĻ āϤā§āϰā§āĻāĻŋāϰ āĻāĻžāϰāĻŖā§ āϏā§āĻāĻžāĻ āĻ āĻŋāĻāĻ āĻžāĻ āĻšā§āύāĻŋāĨ¤
EEE Lab Exam: āϏāĻŦāĻžāĻāĻā§ āĻŦāϞāĻŦā§āύ āϏāĻžāĻŽāύā§āϰ āĻā§āϞāĻžāϏ⧠āϞā§āϝāĻžāĻŦ āĻĒāϰā§āĻā§āώāĻž āĻšāĻŦā§ āĻāĻŦāĻ full wave rectifier āĻāĻžāϞ āĻāϰ⧠āĻĒā§āĻžāĻļā§āύāĻž āĻāϰ⧠āĻāϏāĻŦā§āύ āĻāĻŦāĻ youtube āĻ oscilloscope āĻŦā§āϝāĻžāĻŦāĻšāĻžāϰ āĻŦāĻŋāϧāĻŋ āĻāĻžāϞ āĻāϰ⧠āĻļāĻŋāĻā§ āĻāϏāĻŦā§āύāĨ¤ -
EEE Theory:Âļ
- Zener diode, PNP and NPN Junction, Emitter, Collector, Base.
- Assignment Reminder: āϝāĻžāϰāĻž āĻāĻāύāĻ āĻāĻā§āϰ assignment āĻĻā§āύāύāĻŋ āϤāĻžāϰāĻž āĻĻāĻŋā§ā§ āĻĻāĻŋāĻŦā§āύāĨ¤
-
Bangladesh Studies:Âļ
Subject: Assignment SubmissionÂļ
Topic: The Ancient Trade of India with Rome
Length: 2000 â 2500 words
Date: 20th September
Deadline: 26th SeptemberAssignment instructions:Âļ
- Introduction (āĻā§āĻŽāĻŋāĻāĻž)
- Topic-āĻāϰ āϏāĻāĻā§āώāĻŋāĻĒā§āϤ āĻĒāϰāĻŋāĻā§ āĻ āĻā§āϰā§āϤā§āĻŦ
- Historical Background (āĻāϤāĻŋāĻšāĻžāϏāĻŋāĻ āĻĒā§āϰā§āĻā§āώāĻžāĻĒāĻ)
- Political context of India and Rome
- āϏāĻŽāϏāĻžāĻŽā§āĻŋāĻ āϰāĻžāĻāύā§āϤāĻŋ, āĻļāĻžāϏāύ āĻŦā§āϝāĻŦāϏā§āĻĨāĻž āĻ āĻāϤāĻŋāĻšāĻžāϏāĻŋāĻ āĻāĻāύāĻž
- Ancient Trade (āĻĒā§āϰāĻžāĻā§āύ āĻŦāĻžāĻŖāĻŋāĻā§āϝ āϏāĻŽā§āĻĒāϰā§āĻ)
- Nature of trade (land route & sea route)
- āĻĒā§āϰāϧāĻžāύ āĻŦāĻžāĻŖāĻŋāĻā§āϝ āĻā§āύā§āĻĻā§āϰ āĻ āĻŦāύā§āĻĻāϰ
- Trade theories and historical evidence
- Economical Context (āĻ āϰā§āĻĨāύā§āϤāĻŋāĻ āĻĒā§āϰā§āĻā§āώāĻžāĻĒāĻ)
- Indo-Roman trade āĻāϰ āĻ āϰā§āĻĨāύā§āϤāĻŋāĻ āĻĒā§āϰāĻāĻžāĻŦ
- ImportâExport Analysis (āĻāĻŽāĻĻāĻžāύāĻŋâāϰāĻĒā§āϤāĻžāύāĻŋ āĻŦāĻŋāĻļā§āϞā§āώāĻŖ)
- Exports from India â Spices, textiles, pearls, ivory, silk
- Imports from Rome â Wine, coral, olive oil, luxury items
- Balance of trade discussion
- Conclusion (āĻāĻĒāϏāĻāĻšāĻžāϰ)
Note: āĻšāĻžāϤ⧠āϞāĻŋāĻāϤ⧠āĻšāĻŦā§āĨ¤
Bangladesh Studies Exam
Exam Topics (Short Questions):
1. History â Necessity of History
2. State â Characteristics of Modern State
3. Pal Era
4. Sen Era
5. Context of Muslim Expedition in India
6. Independent Sultanate of Bengal
7. Expedition of Bengal by Bakhtiar Khiljiđ Note:
* āĻĒāϰā§āĻā§āώāĻžā§ āĻļā§āϧā§āĻŽāĻžāϤā§āϰ āĻ āϞā§āĻĒ āύāĻŽā§āĻŦāϰā§āϰ Short Questions āĻĨāĻžāĻāĻŦā§āĨ¤
* āĻāĻĒāϰā§āĻā§āϤ āĻŦāĻŋāώā§āĻā§āϞ⧠āĻĨā§āĻā§ āĻĒā§āϰāĻļā§āύ āĻāϰāĻž āĻšāĻŦā§āĨ¤
26-27 SEPT 2025
đ´āĻāĻāĻžāĻŽā§ ā§§ā§§āϤāĻžāϰāĻŋāĻ SPL Exam āĻšāĻŦā§āĨ¤
Exam Topic:āĻļā§āϰ⧠āĻĨā§āĻā§ Loop āĻĒāϰā§āϝāύā§āϤ āϏā§āϝāĻžāϰ āϝāĻž āĻĒā§āĻŋā§ā§āĻā§āύāĨ¤
đ´SPL Theory Assignment:
āϏā§āϝāĻžāϰ āĻāĻ āĻĒāϰā§āϝāύā§āϤ āϝāĻž āĻĒā§āĻŋā§ā§āĻā§āύ āϤāĻžāϰ āĻŽāϧā§āϝ⧠āĻĨā§āĻā§ ā§§ā§ĻāĻāĻž Question āύāĻŋāĻā§āϰ āĻŽāϤ⧠āĻāϰ⧠āĻŦāĻžāύāĻŋā§ā§ āϏā§āĻā§āϞā§āϰ Answer āϤā§āϰāĻŋ āĻāϰāϤ⧠āĻšāĻŦā§āĨ¤
Deadline:11 October
đ´SPL Lab Assignment:
āĻāĻ āĻĒāϰā§āϝāύā§āϤ āϝāϤ āĻāĻĒāĻŋāĻā§āϰ āĻāĻĒāϰ āϞā§āϝāĻžāĻŦ āĻšā§ā§āĻā§ āϤāĻžāϰ āĻŽāϧā§āϝ āĻĨā§āĻā§ ā§§ā§ĻāĻāĻž āĻĒā§āϰā§āĻā§āϰāĻžāĻŽ āĻŦāĻžāύāĻŋā§ā§ PowerPoint āĻ āĻĒā§āϏā§āĻ āĻāϰāϤ⧠āĻšāĻŦā§āĨ¤āϝ⧠āĻĒā§āϰā§āĻā§āϰāĻžāĻŽ āĻāϰā§āĻā§āύ āϏā§āĻāĻžāύ⧠āϝāĻž āĻāĻŋāĻā§ āĻāĻāĻ āĻāϰā§āĻā§āύ āϤāĻžāϰ āϏāĻŽā§āĻĒāϰā§āĻā§ āϞāĻŋāĻāĻŦā§āύ(āϝā§āĻŽāύ: āĻāĻāĻāĻž āĻĒā§āϰā§āĻā§āϰāĻžāĻŽ āĻ āĻāĻāĻ āĻāϰā§āĻā§āύ for loop. āĻĒā§āϰā§āĻā§āϰāĻžāĻŽ āĻāϰ āύāĻŋāĻā§ for loop āĻāĻŋ āĻā§āύ⧠āĻāĻāϏ āĻāϰāϤ⧠āĻšā§āĨ¤ āĻāĻāĻžā§āĻž int, main āϝāĻžāĻāĻŋāĻā§ āĻĒā§āϰā§āĻā§āϰāĻžāĻŽ āĻ āĻāĻāĻ āĻāϰāĻŦā§āύ āϤāĻžāϰ āϏāĻŽā§āĻĒāϰā§āĻā§ āϞāĻŋāĻāĻŦā§āύ)āĨ¤ Presentation āĻāϰ āĻŽāϤ⧠āĻāϰ⧠āĻāϰāϤ⧠āĻšāĻŦā§āĨ¤
Deadline:11 October.
đ´ā§§ā§§ āϤāĻžāϰāĻŋāĻ SPL Lab āĻāĻā§āϏāĻžāĻŽ āĻšāĻŦā§āĨ¤
Lab Exam Topic:āĻļā§āϰ⧠āĻĨā§āĻā§ Loop āĻĒāϰā§āϝāύā§āϤ āϝāϤ āĻāĻĒāĻŋāĻā§āϰ āĻāĻĒāϰ āϞā§āϝāĻžāĻŦ āĻā§āϞāĻžāϏ āĻšā§ā§āĻā§āĨ¤
All DLD Lab Lists:
āϏāĻŦāĻā§āϞ⧠circuit solve āĻāϰ⧠TinkerCad āĻ submit āĻāϰāϤ⧠āĻšāĻŦā§āĨ¤
1.1: OR Gate
1.2: AND Gate
1.3: NOT Gate
3.1: NAND -> NOT, OR, AND āĻĻāĻŋā§ā§
3.2: NOR -> NOT, OR, AND āĻĻāĻŋā§ā§
3.3: NAND -> XNOR, XOR āĻĻāĻŋā§ā§
3.3: NOR -> XNOR, XOR āĻĻāĻŋā§ā§
4 (Circuit Design with K-Map solution )
4.1: Minterms: âM(1, 2, 4, 5, 7)
4.2: Minterms: âM(2,3,6,7,8,10,13,15)
4.3: Maxterms: Î M(1, 2, 4, 5, 7)
4.4: Maxterms: Î M(2,3,6,7,8,10,13,15)
5.1: Half Adder āĻĻāĻŋā§ā§ circuit āĻāϰ⧠TinkerCad āĻ submit āĻāϰāϤ⧠āĻšāĻŦā§āĨ¤
5.2: Half Subtractor āĻĻāĻŋā§ā§ circuit āĻāϰ⧠TinkerCad āĻ submit āĻāϰāϤ⧠āĻšāĻŦā§āĨ¤
6.1: Full Adder āĻĻāĻŋā§ā§ circuit āĻāϰ⧠TinkerCad āĻ submit āĻāϰāϤ⧠āĻšāĻŦā§āĨ¤
6.2: Full Subtractor āĻĻāĻŋā§ā§ circuit āĻāϰ⧠TinkerCad āĻ submit āĻāϰāϤ⧠āĻšāĻŦā§āĨ¤
7.1: 2-4 Decoder
7.2: 3-8 Decoder (Using two 2-4 decoder)
7.3: Encoder
